1*0fca6ea1SDimitry Andric //===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===// 2*0fca6ea1SDimitry Andric // 3*0fca6ea1SDimitry Andric // The LLVM Compiler Infrastructure 4*0fca6ea1SDimitry Andric // 5*0fca6ea1SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6*0fca6ea1SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 7*0fca6ea1SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8*0fca6ea1SDimitry Andric // 9*0fca6ea1SDimitry Andric //===----------------------------------------------------------------------===// 10*0fca6ea1SDimitry Andric // 11*0fca6ea1SDimitry Andric // This file contains the Xtensa implementation of the TargetInstrInfo class. 12*0fca6ea1SDimitry Andric // 13*0fca6ea1SDimitry Andric //===----------------------------------------------------------------------===// 14*0fca6ea1SDimitry Andric 15*0fca6ea1SDimitry Andric #ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 16*0fca6ea1SDimitry Andric #define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 17*0fca6ea1SDimitry Andric 18*0fca6ea1SDimitry Andric #include "Xtensa.h" 19*0fca6ea1SDimitry Andric #include "XtensaRegisterInfo.h" 20*0fca6ea1SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 21*0fca6ea1SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 22*0fca6ea1SDimitry Andric 23*0fca6ea1SDimitry Andric #define GET_INSTRINFO_HEADER 24*0fca6ea1SDimitry Andric 25*0fca6ea1SDimitry Andric #include "XtensaGenInstrInfo.inc" 26*0fca6ea1SDimitry Andric 27*0fca6ea1SDimitry Andric namespace llvm { 28*0fca6ea1SDimitry Andric 29*0fca6ea1SDimitry Andric class XtensaTargetMachine; 30*0fca6ea1SDimitry Andric class XtensaSubtarget; 31*0fca6ea1SDimitry Andric class XtensaInstrInfo : public XtensaGenInstrInfo { 32*0fca6ea1SDimitry Andric const XtensaRegisterInfo RI; 33*0fca6ea1SDimitry Andric const XtensaSubtarget &STI; 34*0fca6ea1SDimitry Andric 35*0fca6ea1SDimitry Andric public: 36*0fca6ea1SDimitry Andric XtensaInstrInfo(const XtensaSubtarget &STI); 37*0fca6ea1SDimitry Andric 38*0fca6ea1SDimitry Andric void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 39*0fca6ea1SDimitry Andric MachineBasicBlock::iterator I) const; 40*0fca6ea1SDimitry Andric 41*0fca6ea1SDimitry Andric // Return the XtensaRegisterInfo, which this class owns. 42*0fca6ea1SDimitry Andric const XtensaRegisterInfo &getRegisterInfo() const { return RI; } 43*0fca6ea1SDimitry Andric 44*0fca6ea1SDimitry Andric Register isLoadFromStackSlot(const MachineInstr &MI, 45*0fca6ea1SDimitry Andric int &FrameIndex) const override; 46*0fca6ea1SDimitry Andric 47*0fca6ea1SDimitry Andric Register isStoreToStackSlot(const MachineInstr &MI, 48*0fca6ea1SDimitry Andric int &FrameIndex) const override; 49*0fca6ea1SDimitry Andric 50*0fca6ea1SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 51*0fca6ea1SDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 52*0fca6ea1SDimitry Andric bool KillSrc) const override; 53*0fca6ea1SDimitry Andric 54*0fca6ea1SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 55*0fca6ea1SDimitry Andric MachineBasicBlock::iterator MBBI, Register SrcReg, 56*0fca6ea1SDimitry Andric bool isKill, int FrameIndex, 57*0fca6ea1SDimitry Andric const TargetRegisterClass *RC, 58*0fca6ea1SDimitry Andric const TargetRegisterInfo *TRI, 59*0fca6ea1SDimitry Andric Register VReg) const override; 60*0fca6ea1SDimitry Andric 61*0fca6ea1SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 62*0fca6ea1SDimitry Andric MachineBasicBlock::iterator MBBI, Register DestReg, 63*0fca6ea1SDimitry Andric int FrameIdx, const TargetRegisterClass *RC, 64*0fca6ea1SDimitry Andric const TargetRegisterInfo *TRI, 65*0fca6ea1SDimitry Andric Register VReg) const override; 66*0fca6ea1SDimitry Andric 67*0fca6ea1SDimitry Andric // Get the load and store opcodes for a given register class and offset. 68*0fca6ea1SDimitry Andric void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, 69*0fca6ea1SDimitry Andric unsigned &StoreOpcode, int64_t offset) const; 70*0fca6ea1SDimitry Andric 71*0fca6ea1SDimitry Andric // Emit code before MBBI in MI to move immediate value Value into 72*0fca6ea1SDimitry Andric // physical register Reg. 73*0fca6ea1SDimitry Andric void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 74*0fca6ea1SDimitry Andric unsigned *Reg, int64_t Value) const; 75*0fca6ea1SDimitry Andric 76*0fca6ea1SDimitry Andric const XtensaSubtarget &getSubtarget() const { return STI; } 77*0fca6ea1SDimitry Andric }; 78*0fca6ea1SDimitry Andric } // end namespace llvm 79*0fca6ea1SDimitry Andric 80*0fca6ea1SDimitry Andric #endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */ 81