1e8d8bef9SDimitry Andric//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===// 2e8d8bef9SDimitry Andric// 3e8d8bef9SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric// 7e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric// 9e8d8bef9SDimitry Andric// This file describes the instructions that make up the AMD Secure Nested 10e8d8bef9SDimitry Andric// Paging (SNP) instruction set. 11e8d8bef9SDimitry Andric// 12e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 13e8d8bef9SDimitry Andric 14e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 15e8d8bef9SDimitry Andric// SNP instructions 16e8d8bef9SDimitry Andric 17e8d8bef9SDimitry Andriclet SchedRW = [WriteSystem] in { 18e8d8bef9SDimitry Andric// F3 0F 01 FF 1906c3fb27SDimitry Andriclet Uses = [RAX], Defs = [EAX, EFLAGS] in 20*cb14a3feSDimitry Andricdef PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, TB, XS, 21e8d8bef9SDimitry Andric Requires<[In64BitMode]>; 22e8d8bef9SDimitry Andric 23e8d8bef9SDimitry Andric// F2 0F 01 FF 2406c3fb27SDimitry Andriclet Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in 25e8d8bef9SDimitry Andricdef PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, 26*cb14a3feSDimitry Andric TB, XD, Requires<[In64BitMode]>; 27e8d8bef9SDimitry Andric 2806c3fb27SDimitry Andriclet Uses = [EAX, ECX, EDX], Defs = [EAX, EFLAGS] in 29e8d8bef9SDimitry Andricdef PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, 30*cb14a3feSDimitry Andric TB, XD, Requires<[Not64BitMode]>; 31e8d8bef9SDimitry Andric 32e8d8bef9SDimitry Andric// F2 0F 01 FE 3306c3fb27SDimitry Andriclet Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in 34*cb14a3feSDimitry Andricdef RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, TB, XD, 35e8d8bef9SDimitry Andric Requires<[In64BitMode]>; 36e8d8bef9SDimitry Andric 37e8d8bef9SDimitry Andric// F3 0F 01 FE 3806c3fb27SDimitry Andriclet Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in 39*cb14a3feSDimitry Andricdef RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, TB, XS, 40e8d8bef9SDimitry Andric Requires<[In64BitMode]>; 4106c3fb27SDimitry Andric 4206c3fb27SDimitry Andric// F3 0F 01 FD 4306c3fb27SDimitry Andriclet Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in 44*cb14a3feSDimitry Andricdef RMPQUERY: I<0x01, MRM_FD, (outs), (ins), "rmpquery", []>, TB, XS, 4506c3fb27SDimitry Andric Requires<[In64BitMode]>; 46e8d8bef9SDimitry Andric} // SchedRW 47e8d8bef9SDimitry Andric 48e8d8bef9SDimitry Andricdef : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>; 4906c3fb27SDimitry Andricdef : InstAlias<"pvalidate\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (PVALIDATE64)>, Requires<[In64BitMode]>; 5006c3fb27SDimitry Andricdef : InstAlias<"pvalidate\t{%eax, %ecx, %edx|edx, ecx, eax|}", (PVALIDATE32)>, Requires<[Not64BitMode]>; 5106c3fb27SDimitry Andricdef : InstAlias<"rmpupdate\t{%rax, %rcx|rcx, rax|}", (RMPUPDATE)>, Requires<[In64BitMode]>; 5206c3fb27SDimitry Andricdef : InstAlias<"rmpadjust\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (RMPADJUST)>, Requires<[In64BitMode]>; 5306c3fb27SDimitry Andricdef : InstAlias<"rmpquery\t{%rax, %rdx|rdx, rax|}", (RMPQUERY)>, Requires<[In64BitMode]>; 54