15f757f3fSDimitry Andric//===------- X86InstrOperands.td - X86 Operand Definitions --*- tablegen -*-===// 25f757f3fSDimitry Andric// 35f757f3fSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 45f757f3fSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 55f757f3fSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65f757f3fSDimitry Andric// 75f757f3fSDimitry Andric//===----------------------------------------------------------------------===// 85f757f3fSDimitry Andric 95f757f3fSDimitry Andric// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 105f757f3fSDimitry Andric// the index operand of an address, to conform to x86 encoding restrictions. 115f757f3fSDimitry Andricdef ptr_rc_nosp : PointerLikeRegClass<1>; 125f757f3fSDimitry Andric 135f757f3fSDimitry Andric// *mem - Operand definitions for the funky X86 addressing mode operands. 145f757f3fSDimitry Andric// 155f757f3fSDimitry Andricdef X86MemAsmOperand : AsmOperandClass { 165f757f3fSDimitry Andric let Name = "Mem"; 175f757f3fSDimitry Andric} 185f757f3fSDimitry Andriclet RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 195f757f3fSDimitry Andric def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 205f757f3fSDimitry Andric def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 215f757f3fSDimitry Andric def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 225f757f3fSDimitry Andric def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 235f757f3fSDimitry Andric def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 245f757f3fSDimitry Andric def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 255f757f3fSDimitry Andric def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 265f757f3fSDimitry Andric def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 275f757f3fSDimitry Andric // Gather mem operands 285f757f3fSDimitry Andric def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 295f757f3fSDimitry Andric def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } 305f757f3fSDimitry Andric def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } 315f757f3fSDimitry Andric def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } 325f757f3fSDimitry Andric def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } 335f757f3fSDimitry Andric 345f757f3fSDimitry Andric def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 355f757f3fSDimitry Andric def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } 365f757f3fSDimitry Andric def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } 375f757f3fSDimitry Andric def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } 385f757f3fSDimitry Andric def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } 395f757f3fSDimitry Andric def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } 405f757f3fSDimitry Andric def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } 415f757f3fSDimitry Andric def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } 425f757f3fSDimitry Andric def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; } 435f757f3fSDimitry Andric def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; } 445f757f3fSDimitry Andric def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; } 455f757f3fSDimitry Andric 465f757f3fSDimitry Andric def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } 475f757f3fSDimitry Andric} 485f757f3fSDimitry Andric 495f757f3fSDimitry Andricdef X86AbsMemAsmOperand : AsmOperandClass { 505f757f3fSDimitry Andric let Name = "AbsMem"; 515f757f3fSDimitry Andric let SuperClasses = [X86MemAsmOperand]; 525f757f3fSDimitry Andric} 535f757f3fSDimitry Andric 545f757f3fSDimitry Andricclass X86MemOperand<string printMethod, 555f757f3fSDimitry Andric AsmOperandClass parserMatchClass = X86MemAsmOperand, 565f757f3fSDimitry Andric int size = 0> : Operand<iPTR> { 575f757f3fSDimitry Andric let PrintMethod = printMethod; 585f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 595f757f3fSDimitry Andric let ParserMatchClass = parserMatchClass; 605f757f3fSDimitry Andric let OperandType = "OPERAND_MEMORY"; 615f757f3fSDimitry Andric int Size = size; 625f757f3fSDimitry Andric} 635f757f3fSDimitry Andric 645f757f3fSDimitry Andric// Gather mem operands 655f757f3fSDimitry Andricclass X86VMemOperand<RegisterClass RC, string printMethod, 665f757f3fSDimitry Andric AsmOperandClass parserMatchClass, int size = 0> 675f757f3fSDimitry Andric : X86MemOperand<printMethod, parserMatchClass, size> { 685f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 695f757f3fSDimitry Andric} 705f757f3fSDimitry Andric 715f757f3fSDimitry Andricdef anymem : X86MemOperand<"printMemReference">; 725f757f3fSDimitry Andric 735f757f3fSDimitry Andric// FIXME: Right now we allow any size during parsing, but we might want to 745f757f3fSDimitry Andric// restrict to only unsized memory. 755f757f3fSDimitry Andricdef opaquemem : X86MemOperand<"printMemReference">; 765f757f3fSDimitry Andric 775f757f3fSDimitry Andricdef sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; 785f757f3fSDimitry Andric 795f757f3fSDimitry Andricdef i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>; 805f757f3fSDimitry Andricdef i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 815f757f3fSDimitry Andricdef i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 825f757f3fSDimitry Andricdef i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 835f757f3fSDimitry Andricdef i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 845f757f3fSDimitry Andricdef i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 855f757f3fSDimitry Andricdef i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 865f757f3fSDimitry Andricdef f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 875f757f3fSDimitry Andricdef f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 885f757f3fSDimitry Andricdef f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 895f757f3fSDimitry Andricdef f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>; 905f757f3fSDimitry Andricdef f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 915f757f3fSDimitry Andricdef f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 925f757f3fSDimitry Andricdef f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 935f757f3fSDimitry Andric 945f757f3fSDimitry Andric// 32/64 mode specific mem operands 955f757f3fSDimitry Andricdef i512mem_GR16 : X86MemOperand<"printzmmwordmem", X86Mem512_GR16Operand, 512>; 965f757f3fSDimitry Andricdef i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>; 975f757f3fSDimitry Andricdef i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>; 985f757f3fSDimitry Andric 995f757f3fSDimitry Andric// Gather mem operands 1005f757f3fSDimitry Andricdef vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>; 1015f757f3fSDimitry Andricdef vx128mem : X86VMemOperand<VR128, "printxmmwordmem", X86Mem128_RC128Operand, 128>; 1025f757f3fSDimitry Andricdef vx256mem : X86VMemOperand<VR128, "printymmwordmem", X86Mem256_RC128Operand, 256>; 1035f757f3fSDimitry Andricdef vy128mem : X86VMemOperand<VR256, "printxmmwordmem", X86Mem128_RC256Operand, 128>; 1045f757f3fSDimitry Andricdef vy256mem : X86VMemOperand<VR256, "printymmwordmem", X86Mem256_RC256Operand, 256>; 1055f757f3fSDimitry Andric 1065f757f3fSDimitry Andricdef vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand, 64>; 1075f757f3fSDimitry Andricdef vx128xmem : X86VMemOperand<VR128X, "printxmmwordmem", X86Mem128_RC128XOperand, 128>; 1085f757f3fSDimitry Andricdef vx256xmem : X86VMemOperand<VR128X, "printymmwordmem", X86Mem256_RC128XOperand, 256>; 1095f757f3fSDimitry Andricdef vy128xmem : X86VMemOperand<VR256X, "printxmmwordmem", X86Mem128_RC256XOperand, 128>; 1105f757f3fSDimitry Andricdef vy256xmem : X86VMemOperand<VR256X, "printymmwordmem", X86Mem256_RC256XOperand, 256>; 1115f757f3fSDimitry Andricdef vy512xmem : X86VMemOperand<VR256X, "printzmmwordmem", X86Mem512_RC256XOperand, 512>; 1125f757f3fSDimitry Andricdef vz256mem : X86VMemOperand<VR512, "printymmwordmem", X86Mem256_RC512Operand, 256>; 1135f757f3fSDimitry Andricdef vz512mem : X86VMemOperand<VR512, "printzmmwordmem", X86Mem512_RC512Operand, 512>; 1145f757f3fSDimitry Andric 1155f757f3fSDimitry Andricdef shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; 1165f757f3fSDimitry Andricdef ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 1175f757f3fSDimitry Andricdef sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 1185f757f3fSDimitry Andric 1195f757f3fSDimitry Andric// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 1205f757f3fSDimitry Andric// of a plain GPR, so that it doesn't potentially require a REX prefix. 1215f757f3fSDimitry Andricdef ptr_rc_norex : PointerLikeRegClass<2>; 1225f757f3fSDimitry Andricdef ptr_rc_norex_nosp : PointerLikeRegClass<3>; 1235f757f3fSDimitry Andric 1245f757f3fSDimitry Andricdef i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> { 1255f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 1265f757f3fSDimitry Andric SEGMENT_REG); 1275f757f3fSDimitry Andric} 1285f757f3fSDimitry Andric 1295f757f3fSDimitry Andric// GPRs available for tailcall. 1305f757f3fSDimitry Andric// It represents GR32_TC, GR64_TC or GR64_TCW64. 1315f757f3fSDimitry Andricdef ptr_rc_tailcall : PointerLikeRegClass<4>; 1325f757f3fSDimitry Andric 1335f757f3fSDimitry Andric// Special i32mem for addresses of load folding tail calls. These are not 1345f757f3fSDimitry Andric// allowed to use callee-saved registers since they must be scheduled 1355f757f3fSDimitry Andric// after callee-saved register are popped. 1365f757f3fSDimitry Andricdef i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> { 1375f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 1385f757f3fSDimitry Andric i32imm, SEGMENT_REG); 1395f757f3fSDimitry Andric} 1405f757f3fSDimitry Andric 1415f757f3fSDimitry Andric// Special i64mem for addresses of load folding tail calls. These are not 1425f757f3fSDimitry Andric// allowed to use callee-saved registers since they must be scheduled 1435f757f3fSDimitry Andric// after callee-saved register are popped. 1445f757f3fSDimitry Andricdef i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> { 1455f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 1465f757f3fSDimitry Andric ptr_rc_tailcall, i32imm, SEGMENT_REG); 1475f757f3fSDimitry Andric} 1485f757f3fSDimitry Andric 1495f757f3fSDimitry Andric// Special parser to detect 16-bit mode to select 16-bit displacement. 1505f757f3fSDimitry Andricdef X86AbsMem16AsmOperand : AsmOperandClass { 1515f757f3fSDimitry Andric let Name = "AbsMem16"; 1525f757f3fSDimitry Andric let RenderMethod = "addAbsMemOperands"; 1535f757f3fSDimitry Andric let SuperClasses = [X86AbsMemAsmOperand]; 1545f757f3fSDimitry Andric} 1555f757f3fSDimitry Andric 1565f757f3fSDimitry Andric// Branch targets print as pc-relative values. 1575f757f3fSDimitry Andricclass BranchTargetOperand<ValueType ty> : Operand<ty> { 1585f757f3fSDimitry Andric let OperandType = "OPERAND_PCREL"; 1595f757f3fSDimitry Andric let PrintMethod = "printPCRelImm"; 1605f757f3fSDimitry Andric let ParserMatchClass = X86AbsMemAsmOperand; 1615f757f3fSDimitry Andric} 1625f757f3fSDimitry Andric 1635f757f3fSDimitry Andricdef i32imm_brtarget : BranchTargetOperand<i32>; 1645f757f3fSDimitry Andricdef i16imm_brtarget : BranchTargetOperand<i16>; 1655f757f3fSDimitry Andric 1665f757f3fSDimitry Andric// 64-bits but only 32 bits are significant, and those bits are treated as being 1675f757f3fSDimitry Andric// pc relative. 1685f757f3fSDimitry Andricdef i64i32imm_brtarget : BranchTargetOperand<i64>; 1695f757f3fSDimitry Andric 1705f757f3fSDimitry Andricdef brtarget : BranchTargetOperand<OtherVT>; 1715f757f3fSDimitry Andricdef brtarget8 : BranchTargetOperand<OtherVT>; 1725f757f3fSDimitry Andricdef brtarget16 : BranchTargetOperand<OtherVT> { 1735f757f3fSDimitry Andric let ParserMatchClass = X86AbsMem16AsmOperand; 1745f757f3fSDimitry Andric} 1755f757f3fSDimitry Andricdef brtarget32 : BranchTargetOperand<OtherVT>; 1765f757f3fSDimitry Andric 1775f757f3fSDimitry Andriclet RenderMethod = "addSrcIdxOperands" in { 1785f757f3fSDimitry Andric def X86SrcIdx8Operand : AsmOperandClass { 1795f757f3fSDimitry Andric let Name = "SrcIdx8"; 1805f757f3fSDimitry Andric let SuperClasses = [X86Mem8AsmOperand]; 1815f757f3fSDimitry Andric } 1825f757f3fSDimitry Andric def X86SrcIdx16Operand : AsmOperandClass { 1835f757f3fSDimitry Andric let Name = "SrcIdx16"; 1845f757f3fSDimitry Andric let SuperClasses = [X86Mem16AsmOperand]; 1855f757f3fSDimitry Andric } 1865f757f3fSDimitry Andric def X86SrcIdx32Operand : AsmOperandClass { 1875f757f3fSDimitry Andric let Name = "SrcIdx32"; 1885f757f3fSDimitry Andric let SuperClasses = [X86Mem32AsmOperand]; 1895f757f3fSDimitry Andric } 1905f757f3fSDimitry Andric def X86SrcIdx64Operand : AsmOperandClass { 1915f757f3fSDimitry Andric let Name = "SrcIdx64"; 1925f757f3fSDimitry Andric let SuperClasses = [X86Mem64AsmOperand]; 1935f757f3fSDimitry Andric } 1945f757f3fSDimitry Andric} // RenderMethod = "addSrcIdxOperands" 1955f757f3fSDimitry Andric 1965f757f3fSDimitry Andriclet RenderMethod = "addDstIdxOperands" in { 1975f757f3fSDimitry Andric def X86DstIdx8Operand : AsmOperandClass { 1985f757f3fSDimitry Andric let Name = "DstIdx8"; 1995f757f3fSDimitry Andric let SuperClasses = [X86Mem8AsmOperand]; 2005f757f3fSDimitry Andric } 2015f757f3fSDimitry Andric def X86DstIdx16Operand : AsmOperandClass { 2025f757f3fSDimitry Andric let Name = "DstIdx16"; 2035f757f3fSDimitry Andric let SuperClasses = [X86Mem16AsmOperand]; 2045f757f3fSDimitry Andric } 2055f757f3fSDimitry Andric def X86DstIdx32Operand : AsmOperandClass { 2065f757f3fSDimitry Andric let Name = "DstIdx32"; 2075f757f3fSDimitry Andric let SuperClasses = [X86Mem32AsmOperand]; 2085f757f3fSDimitry Andric } 2095f757f3fSDimitry Andric def X86DstIdx64Operand : AsmOperandClass { 2105f757f3fSDimitry Andric let Name = "DstIdx64"; 2115f757f3fSDimitry Andric let SuperClasses = [X86Mem64AsmOperand]; 2125f757f3fSDimitry Andric } 2135f757f3fSDimitry Andric} // RenderMethod = "addDstIdxOperands" 2145f757f3fSDimitry Andric 2155f757f3fSDimitry Andriclet RenderMethod = "addMemOffsOperands" in { 2165f757f3fSDimitry Andric def X86MemOffs16_8AsmOperand : AsmOperandClass { 2175f757f3fSDimitry Andric let Name = "MemOffs16_8"; 2185f757f3fSDimitry Andric let SuperClasses = [X86Mem8AsmOperand]; 2195f757f3fSDimitry Andric } 2205f757f3fSDimitry Andric def X86MemOffs16_16AsmOperand : AsmOperandClass { 2215f757f3fSDimitry Andric let Name = "MemOffs16_16"; 2225f757f3fSDimitry Andric let SuperClasses = [X86Mem16AsmOperand]; 2235f757f3fSDimitry Andric } 2245f757f3fSDimitry Andric def X86MemOffs16_32AsmOperand : AsmOperandClass { 2255f757f3fSDimitry Andric let Name = "MemOffs16_32"; 2265f757f3fSDimitry Andric let SuperClasses = [X86Mem32AsmOperand]; 2275f757f3fSDimitry Andric } 2285f757f3fSDimitry Andric def X86MemOffs32_8AsmOperand : AsmOperandClass { 2295f757f3fSDimitry Andric let Name = "MemOffs32_8"; 2305f757f3fSDimitry Andric let SuperClasses = [X86Mem8AsmOperand]; 2315f757f3fSDimitry Andric } 2325f757f3fSDimitry Andric def X86MemOffs32_16AsmOperand : AsmOperandClass { 2335f757f3fSDimitry Andric let Name = "MemOffs32_16"; 2345f757f3fSDimitry Andric let SuperClasses = [X86Mem16AsmOperand]; 2355f757f3fSDimitry Andric } 2365f757f3fSDimitry Andric def X86MemOffs32_32AsmOperand : AsmOperandClass { 2375f757f3fSDimitry Andric let Name = "MemOffs32_32"; 2385f757f3fSDimitry Andric let SuperClasses = [X86Mem32AsmOperand]; 2395f757f3fSDimitry Andric } 2405f757f3fSDimitry Andric def X86MemOffs32_64AsmOperand : AsmOperandClass { 2415f757f3fSDimitry Andric let Name = "MemOffs32_64"; 2425f757f3fSDimitry Andric let SuperClasses = [X86Mem64AsmOperand]; 2435f757f3fSDimitry Andric } 2445f757f3fSDimitry Andric def X86MemOffs64_8AsmOperand : AsmOperandClass { 2455f757f3fSDimitry Andric let Name = "MemOffs64_8"; 2465f757f3fSDimitry Andric let SuperClasses = [X86Mem8AsmOperand]; 2475f757f3fSDimitry Andric } 2485f757f3fSDimitry Andric def X86MemOffs64_16AsmOperand : AsmOperandClass { 2495f757f3fSDimitry Andric let Name = "MemOffs64_16"; 2505f757f3fSDimitry Andric let SuperClasses = [X86Mem16AsmOperand]; 2515f757f3fSDimitry Andric } 2525f757f3fSDimitry Andric def X86MemOffs64_32AsmOperand : AsmOperandClass { 2535f757f3fSDimitry Andric let Name = "MemOffs64_32"; 2545f757f3fSDimitry Andric let SuperClasses = [X86Mem32AsmOperand]; 2555f757f3fSDimitry Andric } 2565f757f3fSDimitry Andric def X86MemOffs64_64AsmOperand : AsmOperandClass { 2575f757f3fSDimitry Andric let Name = "MemOffs64_64"; 2585f757f3fSDimitry Andric let SuperClasses = [X86Mem64AsmOperand]; 2595f757f3fSDimitry Andric } 2605f757f3fSDimitry Andric} // RenderMethod = "addMemOffsOperands" 2615f757f3fSDimitry Andric 2625f757f3fSDimitry Andricclass X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 2635f757f3fSDimitry Andric : X86MemOperand<printMethod, parserMatchClass> { 2645f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 2655f757f3fSDimitry Andric} 2665f757f3fSDimitry Andric 2675f757f3fSDimitry Andricclass X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 2685f757f3fSDimitry Andric : X86MemOperand<printMethod, parserMatchClass> { 2695f757f3fSDimitry Andric let MIOperandInfo = (ops ptr_rc); 2705f757f3fSDimitry Andric} 2715f757f3fSDimitry Andric 2725f757f3fSDimitry Andricdef srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 2735f757f3fSDimitry Andricdef srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 2745f757f3fSDimitry Andricdef srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 2755f757f3fSDimitry Andricdef srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 2765f757f3fSDimitry Andricdef dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 2775f757f3fSDimitry Andricdef dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 2785f757f3fSDimitry Andricdef dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 2795f757f3fSDimitry Andricdef dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 2805f757f3fSDimitry Andric 2815f757f3fSDimitry Andricclass X86MemOffsOperand<Operand immOperand, string printMethod, 2825f757f3fSDimitry Andric AsmOperandClass parserMatchClass> 2835f757f3fSDimitry Andric : X86MemOperand<printMethod, parserMatchClass> { 2845f757f3fSDimitry Andric let MIOperandInfo = (ops immOperand, SEGMENT_REG); 2855f757f3fSDimitry Andric} 2865f757f3fSDimitry Andric 2875f757f3fSDimitry Andricdef offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 2885f757f3fSDimitry Andric X86MemOffs16_8AsmOperand>; 2895f757f3fSDimitry Andricdef offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 2905f757f3fSDimitry Andric X86MemOffs16_16AsmOperand>; 2915f757f3fSDimitry Andricdef offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 2925f757f3fSDimitry Andric X86MemOffs16_32AsmOperand>; 2935f757f3fSDimitry Andricdef offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 2945f757f3fSDimitry Andric X86MemOffs32_8AsmOperand>; 2955f757f3fSDimitry Andricdef offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 2965f757f3fSDimitry Andric X86MemOffs32_16AsmOperand>; 2975f757f3fSDimitry Andricdef offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 2985f757f3fSDimitry Andric X86MemOffs32_32AsmOperand>; 2995f757f3fSDimitry Andricdef offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 3005f757f3fSDimitry Andric X86MemOffs32_64AsmOperand>; 3015f757f3fSDimitry Andricdef offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 3025f757f3fSDimitry Andric X86MemOffs64_8AsmOperand>; 3035f757f3fSDimitry Andricdef offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 3045f757f3fSDimitry Andric X86MemOffs64_16AsmOperand>; 3055f757f3fSDimitry Andricdef offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 3065f757f3fSDimitry Andric X86MemOffs64_32AsmOperand>; 3075f757f3fSDimitry Andricdef offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 3085f757f3fSDimitry Andric X86MemOffs64_64AsmOperand>; 3095f757f3fSDimitry Andric 3105f757f3fSDimitry Andricdef ccode : Operand<i8> { 3115f757f3fSDimitry Andric let PrintMethod = "printCondCode"; 3125f757f3fSDimitry Andric let OperandNamespace = "X86"; 3135f757f3fSDimitry Andric let OperandType = "OPERAND_COND_CODE"; 3145f757f3fSDimitry Andric} 3155f757f3fSDimitry Andric 3165f757f3fSDimitry Andricclass ImmSExtAsmOperandClass : AsmOperandClass { 3175f757f3fSDimitry Andric let SuperClasses = [ImmAsmOperand]; 3185f757f3fSDimitry Andric let RenderMethod = "addImmOperands"; 3195f757f3fSDimitry Andric} 3205f757f3fSDimitry Andric 3215f757f3fSDimitry Andricdef X86GR32orGR64AsmOperand : AsmOperandClass { 3225f757f3fSDimitry Andric let Name = "GR32orGR64"; 3235f757f3fSDimitry Andric} 3245f757f3fSDimitry Andricdef GR32orGR64 : RegisterOperand<GR32> { 3255f757f3fSDimitry Andric let ParserMatchClass = X86GR32orGR64AsmOperand; 3265f757f3fSDimitry Andric} 3275f757f3fSDimitry Andric 3285f757f3fSDimitry Andricdef X86GR16orGR32orGR64AsmOperand : AsmOperandClass { 3295f757f3fSDimitry Andric let Name = "GR16orGR32orGR64"; 3305f757f3fSDimitry Andric} 3315f757f3fSDimitry Andricdef GR16orGR32orGR64 : RegisterOperand<GR16> { 3325f757f3fSDimitry Andric let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; 3335f757f3fSDimitry Andric} 3345f757f3fSDimitry Andric 3355f757f3fSDimitry Andricdef AVX512RCOperand : AsmOperandClass { 3365f757f3fSDimitry Andric let Name = "AVX512RC"; 3375f757f3fSDimitry Andric} 3385f757f3fSDimitry Andricdef AVX512RC : Operand<i32> { 3395f757f3fSDimitry Andric let PrintMethod = "printRoundingControl"; 3405f757f3fSDimitry Andric let OperandNamespace = "X86"; 3415f757f3fSDimitry Andric let OperandType = "OPERAND_ROUNDING_CONTROL"; 3425f757f3fSDimitry Andric let ParserMatchClass = AVX512RCOperand; 3435f757f3fSDimitry Andric} 3445f757f3fSDimitry Andric 3455f757f3fSDimitry Andric// Sign-extended immediate classes. We don't need to define the full lattice 3465f757f3fSDimitry Andric// here because there is no instruction with an ambiguity between ImmSExti64i32 3475f757f3fSDimitry Andric// and ImmSExti32i8. 3485f757f3fSDimitry Andric// 3495f757f3fSDimitry Andric// The strange ranges come from the fact that the assembler always works with 3505f757f3fSDimitry Andric// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 3515f757f3fSDimitry Andric// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 3525f757f3fSDimitry Andric 3535f757f3fSDimitry Andric// [0, 0x7FFFFFFF] | 3545f757f3fSDimitry Andric// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 3555f757f3fSDimitry Andricdef ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 3565f757f3fSDimitry Andric let Name = "ImmSExti64i32"; 3575f757f3fSDimitry Andric} 3585f757f3fSDimitry Andric 3595f757f3fSDimitry Andric// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 3605f757f3fSDimitry Andric// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 3615f757f3fSDimitry Andricdef ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 3625f757f3fSDimitry Andric let Name = "ImmSExti16i8"; 3635f757f3fSDimitry Andric let SuperClasses = [ImmSExti64i32AsmOperand]; 3645f757f3fSDimitry Andric} 3655f757f3fSDimitry Andric 3665f757f3fSDimitry Andric// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 3675f757f3fSDimitry Andric// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 3685f757f3fSDimitry Andricdef ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 3695f757f3fSDimitry Andric let Name = "ImmSExti32i8"; 3705f757f3fSDimitry Andric} 3715f757f3fSDimitry Andric 3725f757f3fSDimitry Andric// [0, 0x0000007F] | 3735f757f3fSDimitry Andric// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 3745f757f3fSDimitry Andricdef ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 3755f757f3fSDimitry Andric let Name = "ImmSExti64i8"; 3765f757f3fSDimitry Andric let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 3775f757f3fSDimitry Andric ImmSExti64i32AsmOperand]; 3785f757f3fSDimitry Andric} 3795f757f3fSDimitry Andric 3805f757f3fSDimitry Andric// 4-bit immediate used by some XOP instructions 3815f757f3fSDimitry Andric// [0, 0xF] 3825f757f3fSDimitry Andricdef ImmUnsignedi4AsmOperand : AsmOperandClass { 3835f757f3fSDimitry Andric let Name = "ImmUnsignedi4"; 3845f757f3fSDimitry Andric let RenderMethod = "addImmOperands"; 3855f757f3fSDimitry Andric let DiagnosticType = "InvalidImmUnsignedi4"; 3865f757f3fSDimitry Andric} 3875f757f3fSDimitry Andric 3885f757f3fSDimitry Andric// Unsigned immediate used by SSE/AVX instructions 3895f757f3fSDimitry Andric// [0, 0xFF] 3905f757f3fSDimitry Andric// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 3915f757f3fSDimitry Andricdef ImmUnsignedi8AsmOperand : AsmOperandClass { 3925f757f3fSDimitry Andric let Name = "ImmUnsignedi8"; 3935f757f3fSDimitry Andric let RenderMethod = "addImmOperands"; 3945f757f3fSDimitry Andric} 3955f757f3fSDimitry Andric 3965f757f3fSDimitry Andric// A couple of more descriptive operand definitions. 3975f757f3fSDimitry Andric// 16-bits but only 8 bits are significant. 3985f757f3fSDimitry Andricdef i16i8imm : Operand<i16> { 3995f757f3fSDimitry Andric let ParserMatchClass = ImmSExti16i8AsmOperand; 4005f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4015f757f3fSDimitry Andric} 4025f757f3fSDimitry Andric// 32-bits but only 8 bits are significant. 4035f757f3fSDimitry Andricdef i32i8imm : Operand<i32> { 4045f757f3fSDimitry Andric let ParserMatchClass = ImmSExti32i8AsmOperand; 4055f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4065f757f3fSDimitry Andric} 4075f757f3fSDimitry Andric 4085f757f3fSDimitry Andric// 64-bits but only 32 bits are significant. 4095f757f3fSDimitry Andricdef i64i32imm : Operand<i64> { 4105f757f3fSDimitry Andric let ParserMatchClass = ImmSExti64i32AsmOperand; 4115f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4125f757f3fSDimitry Andric} 4135f757f3fSDimitry Andric 4145f757f3fSDimitry Andric// 64-bits but only 8 bits are significant. 4155f757f3fSDimitry Andricdef i64i8imm : Operand<i64> { 4165f757f3fSDimitry Andric let ParserMatchClass = ImmSExti64i8AsmOperand; 4175f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4185f757f3fSDimitry Andric} 4195f757f3fSDimitry Andric 4205f757f3fSDimitry Andric// Unsigned 4-bit immediate used by some XOP instructions. 4215f757f3fSDimitry Andricdef u4imm : Operand<i8> { 4225f757f3fSDimitry Andric let PrintMethod = "printU8Imm"; 4235f757f3fSDimitry Andric let ParserMatchClass = ImmUnsignedi4AsmOperand; 4245f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4255f757f3fSDimitry Andric} 4265f757f3fSDimitry Andric 427*0fca6ea1SDimitry Andricdef cflags : Operand<i8> { 428*0fca6ea1SDimitry Andric let PrintMethod = "printCondFlags"; 429*0fca6ea1SDimitry Andric let ParserMatchClass = ImmUnsignedi4AsmOperand; 430*0fca6ea1SDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 431*0fca6ea1SDimitry Andric} 432*0fca6ea1SDimitry Andric 4335f757f3fSDimitry Andric// Unsigned 8-bit immediate used by SSE/AVX instructions. 4345f757f3fSDimitry Andricdef u8imm : Operand<i8> { 4355f757f3fSDimitry Andric let PrintMethod = "printU8Imm"; 4365f757f3fSDimitry Andric let ParserMatchClass = ImmUnsignedi8AsmOperand; 4375f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4385f757f3fSDimitry Andric} 4395f757f3fSDimitry Andric 4405f757f3fSDimitry Andric// 16-bit immediate but only 8-bits are significant and they are unsigned. 4415f757f3fSDimitry Andric// Used by BT instructions. 4425f757f3fSDimitry Andricdef i16u8imm : Operand<i16> { 4435f757f3fSDimitry Andric let PrintMethod = "printU8Imm"; 4445f757f3fSDimitry Andric let ParserMatchClass = ImmUnsignedi8AsmOperand; 4455f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4465f757f3fSDimitry Andric} 4475f757f3fSDimitry Andric 4485f757f3fSDimitry Andric// 32-bit immediate but only 8-bits are significant and they are unsigned. 4495f757f3fSDimitry Andric// Used by some SSE/AVX instructions that use intrinsics. 4505f757f3fSDimitry Andricdef i32u8imm : Operand<i32> { 4515f757f3fSDimitry Andric let PrintMethod = "printU8Imm"; 4525f757f3fSDimitry Andric let ParserMatchClass = ImmUnsignedi8AsmOperand; 4535f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4545f757f3fSDimitry Andric} 4555f757f3fSDimitry Andric 4565f757f3fSDimitry Andric// 64-bit immediate but only 8-bits are significant and they are unsigned. 4575f757f3fSDimitry Andric// Used by BT instructions. 4585f757f3fSDimitry Andricdef i64u8imm : Operand<i64> { 4595f757f3fSDimitry Andric let PrintMethod = "printU8Imm"; 4605f757f3fSDimitry Andric let ParserMatchClass = ImmUnsignedi8AsmOperand; 4615f757f3fSDimitry Andric let OperandType = "OPERAND_IMMEDIATE"; 4625f757f3fSDimitry Andric} 4635f757f3fSDimitry Andric 4645f757f3fSDimitry Andricdef lea64_32mem : Operand<i32> { 4655f757f3fSDimitry Andric let PrintMethod = "printMemReference"; 4665f757f3fSDimitry Andric let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 4675f757f3fSDimitry Andric let ParserMatchClass = X86MemAsmOperand; 4685f757f3fSDimitry Andric} 4695f757f3fSDimitry Andric 4705f757f3fSDimitry Andric// Memory operands that use 64-bit pointers in both ILP32 and LP64. 4715f757f3fSDimitry Andricdef lea64mem : Operand<i64> { 4725f757f3fSDimitry Andric let PrintMethod = "printMemReference"; 4735f757f3fSDimitry Andric let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 4745f757f3fSDimitry Andric let ParserMatchClass = X86MemAsmOperand; 4755f757f3fSDimitry Andric} 4765f757f3fSDimitry Andric 4775f757f3fSDimitry Andriclet RenderMethod = "addMaskPairOperands" in { 4785f757f3fSDimitry Andric def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } 4795f757f3fSDimitry Andric def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } 4805f757f3fSDimitry Andric def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } 4815f757f3fSDimitry Andric def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } 4825f757f3fSDimitry Andric def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } 4835f757f3fSDimitry Andric} 4845f757f3fSDimitry Andric 4855f757f3fSDimitry Andricdef VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> { 4865f757f3fSDimitry Andric let ParserMatchClass = VK1PairAsmOperand; 4875f757f3fSDimitry Andric} 4885f757f3fSDimitry Andric 4895f757f3fSDimitry Andricdef VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> { 4905f757f3fSDimitry Andric let ParserMatchClass = VK2PairAsmOperand; 4915f757f3fSDimitry Andric} 4925f757f3fSDimitry Andric 4935f757f3fSDimitry Andricdef VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> { 4945f757f3fSDimitry Andric let ParserMatchClass = VK4PairAsmOperand; 4955f757f3fSDimitry Andric} 4965f757f3fSDimitry Andric 4975f757f3fSDimitry Andricdef VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> { 4985f757f3fSDimitry Andric let ParserMatchClass = VK8PairAsmOperand; 4995f757f3fSDimitry Andric} 5005f757f3fSDimitry Andric 5015f757f3fSDimitry Andricdef VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> { 5025f757f3fSDimitry Andric let ParserMatchClass = VK16PairAsmOperand; 5035f757f3fSDimitry Andric} 504