1*5f757f3fSDimitry Andric //===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==// 2*5f757f3fSDimitry Andric // 3*5f757f3fSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*5f757f3fSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*5f757f3fSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*5f757f3fSDimitry Andric // 7*5f757f3fSDimitry Andric //===----------------------------------------------------------------------===// 8*5f757f3fSDimitry Andric /// \file 9*5f757f3fSDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for X86. 10*5f757f3fSDimitry Andric /// \todo This should be generated by TableGen. 11*5f757f3fSDimitry Andric //===----------------------------------------------------------------------===// 12*5f757f3fSDimitry Andric 13*5f757f3fSDimitry Andric #ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 14*5f757f3fSDimitry Andric #define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 15*5f757f3fSDimitry Andric 16*5f757f3fSDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 17*5f757f3fSDimitry Andric 18*5f757f3fSDimitry Andric #define GET_REGBANK_DECLARATIONS 19*5f757f3fSDimitry Andric #include "X86GenRegisterBank.inc" 20*5f757f3fSDimitry Andric 21*5f757f3fSDimitry Andric namespace llvm { 22*5f757f3fSDimitry Andric 23*5f757f3fSDimitry Andric class LLT; 24*5f757f3fSDimitry Andric 25*5f757f3fSDimitry Andric class X86GenRegisterBankInfo : public RegisterBankInfo { 26*5f757f3fSDimitry Andric protected: 27*5f757f3fSDimitry Andric #define GET_TARGET_REGBANK_CLASS 28*5f757f3fSDimitry Andric #include "X86GenRegisterBank.inc" 29*5f757f3fSDimitry Andric #define GET_TARGET_REGBANK_INFO_CLASS 30*5f757f3fSDimitry Andric #include "X86GenRegisterBankInfo.def" 31*5f757f3fSDimitry Andric 32*5f757f3fSDimitry Andric static RegisterBankInfo::PartialMapping PartMappings[]; 33*5f757f3fSDimitry Andric static RegisterBankInfo::ValueMapping ValMappings[]; 34*5f757f3fSDimitry Andric 35*5f757f3fSDimitry Andric static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP); 36*5f757f3fSDimitry Andric static const RegisterBankInfo::ValueMapping * 37*5f757f3fSDimitry Andric getValueMapping(PartialMappingIdx Idx, unsigned NumOperands); 38*5f757f3fSDimitry Andric }; 39*5f757f3fSDimitry Andric 40*5f757f3fSDimitry Andric class TargetRegisterInfo; 41*5f757f3fSDimitry Andric 42*5f757f3fSDimitry Andric /// This class provides the information for the target register banks. 43*5f757f3fSDimitry Andric class X86RegisterBankInfo final : public X86GenRegisterBankInfo { 44*5f757f3fSDimitry Andric private: 45*5f757f3fSDimitry Andric /// Get an instruction mapping. 46*5f757f3fSDimitry Andric /// \return An InstructionMappings with a statically allocated 47*5f757f3fSDimitry Andric /// OperandsMapping. 48*5f757f3fSDimitry Andric const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI, 49*5f757f3fSDimitry Andric bool isFP) const; 50*5f757f3fSDimitry Andric 51*5f757f3fSDimitry Andric /// Track the bank of each instruction operand(register) 52*5f757f3fSDimitry Andric static void 53*5f757f3fSDimitry Andric getInstrPartialMappingIdxs(const MachineInstr &MI, 54*5f757f3fSDimitry Andric const MachineRegisterInfo &MRI, const bool isFP, 55*5f757f3fSDimitry Andric SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx); 56*5f757f3fSDimitry Andric 57*5f757f3fSDimitry Andric /// Construct the instruction ValueMapping from PartialMappingIdxs 58*5f757f3fSDimitry Andric /// \return true if mapping succeeded. 59*5f757f3fSDimitry Andric static bool 60*5f757f3fSDimitry Andric getInstrValueMapping(const MachineInstr &MI, 61*5f757f3fSDimitry Andric const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx, 62*5f757f3fSDimitry Andric SmallVectorImpl<const ValueMapping *> &OpdsMapping); 63*5f757f3fSDimitry Andric 64*5f757f3fSDimitry Andric public: 65*5f757f3fSDimitry Andric X86RegisterBankInfo(const TargetRegisterInfo &TRI); 66*5f757f3fSDimitry Andric 67*5f757f3fSDimitry Andric const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 68*5f757f3fSDimitry Andric LLT) const override; 69*5f757f3fSDimitry Andric 70*5f757f3fSDimitry Andric InstructionMappings 71*5f757f3fSDimitry Andric getInstrAlternativeMappings(const MachineInstr &MI) const override; 72*5f757f3fSDimitry Andric 73*5f757f3fSDimitry Andric /// See RegisterBankInfo::applyMapping. 74*5f757f3fSDimitry Andric void applyMappingImpl(MachineIRBuilder &Builder, 75*5f757f3fSDimitry Andric const OperandsMapper &OpdMapper) const override; 76*5f757f3fSDimitry Andric 77*5f757f3fSDimitry Andric const InstructionMapping & 78*5f757f3fSDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 79*5f757f3fSDimitry Andric }; 80*5f757f3fSDimitry Andric 81*5f757f3fSDimitry Andric } // namespace llvm 82*5f757f3fSDimitry Andric #endif 83