15f757f3fSDimitry Andric //===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==// 25f757f3fSDimitry Andric // 35f757f3fSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 45f757f3fSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 55f757f3fSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65f757f3fSDimitry Andric // 75f757f3fSDimitry Andric //===----------------------------------------------------------------------===// 85f757f3fSDimitry Andric /// \file 95f757f3fSDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for X86. 105f757f3fSDimitry Andric /// \todo This should be generated by TableGen. 115f757f3fSDimitry Andric //===----------------------------------------------------------------------===// 125f757f3fSDimitry Andric 135f757f3fSDimitry Andric #ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 145f757f3fSDimitry Andric #define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 155f757f3fSDimitry Andric 165f757f3fSDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 175f757f3fSDimitry Andric 185f757f3fSDimitry Andric #define GET_REGBANK_DECLARATIONS 195f757f3fSDimitry Andric #include "X86GenRegisterBank.inc" 205f757f3fSDimitry Andric 215f757f3fSDimitry Andric namespace llvm { 225f757f3fSDimitry Andric 235f757f3fSDimitry Andric class LLT; 245f757f3fSDimitry Andric 255f757f3fSDimitry Andric class X86GenRegisterBankInfo : public RegisterBankInfo { 265f757f3fSDimitry Andric protected: 275f757f3fSDimitry Andric #define GET_TARGET_REGBANK_CLASS 285f757f3fSDimitry Andric #include "X86GenRegisterBank.inc" 295f757f3fSDimitry Andric #define GET_TARGET_REGBANK_INFO_CLASS 305f757f3fSDimitry Andric #include "X86GenRegisterBankInfo.def" 315f757f3fSDimitry Andric 325f757f3fSDimitry Andric static RegisterBankInfo::PartialMapping PartMappings[]; 335f757f3fSDimitry Andric static RegisterBankInfo::ValueMapping ValMappings[]; 345f757f3fSDimitry Andric 35*0fca6ea1SDimitry Andric static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI, 36*0fca6ea1SDimitry Andric const LLT &Ty, bool isFP); 375f757f3fSDimitry Andric static const RegisterBankInfo::ValueMapping * 385f757f3fSDimitry Andric getValueMapping(PartialMappingIdx Idx, unsigned NumOperands); 395f757f3fSDimitry Andric }; 405f757f3fSDimitry Andric 415f757f3fSDimitry Andric class TargetRegisterInfo; 425f757f3fSDimitry Andric 435f757f3fSDimitry Andric /// This class provides the information for the target register banks. 445f757f3fSDimitry Andric class X86RegisterBankInfo final : public X86GenRegisterBankInfo { 455f757f3fSDimitry Andric private: 465f757f3fSDimitry Andric /// Get an instruction mapping. 475f757f3fSDimitry Andric /// \return An InstructionMappings with a statically allocated 485f757f3fSDimitry Andric /// OperandsMapping. 495f757f3fSDimitry Andric const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI, 505f757f3fSDimitry Andric bool isFP) const; 515f757f3fSDimitry Andric 525f757f3fSDimitry Andric /// Track the bank of each instruction operand(register) 535f757f3fSDimitry Andric static void 545f757f3fSDimitry Andric getInstrPartialMappingIdxs(const MachineInstr &MI, 555f757f3fSDimitry Andric const MachineRegisterInfo &MRI, const bool isFP, 565f757f3fSDimitry Andric SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx); 575f757f3fSDimitry Andric 585f757f3fSDimitry Andric /// Construct the instruction ValueMapping from PartialMappingIdxs 595f757f3fSDimitry Andric /// \return true if mapping succeeded. 605f757f3fSDimitry Andric static bool 615f757f3fSDimitry Andric getInstrValueMapping(const MachineInstr &MI, 625f757f3fSDimitry Andric const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx, 635f757f3fSDimitry Andric SmallVectorImpl<const ValueMapping *> &OpdsMapping); 645f757f3fSDimitry Andric 65*0fca6ea1SDimitry Andric // Maximum recursion depth for hasFPConstraints. 66*0fca6ea1SDimitry Andric const unsigned MaxFPRSearchDepth = 2; 67*0fca6ea1SDimitry Andric 68*0fca6ea1SDimitry Andric /// \returns true if \p MI only uses and defines FPRs. 69*0fca6ea1SDimitry Andric bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 70*0fca6ea1SDimitry Andric const TargetRegisterInfo &TRI, 71*0fca6ea1SDimitry Andric unsigned Depth = 0) const; 72*0fca6ea1SDimitry Andric 73*0fca6ea1SDimitry Andric /// \returns true if \p MI only uses FPRs. 74*0fca6ea1SDimitry Andric bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 75*0fca6ea1SDimitry Andric const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 76*0fca6ea1SDimitry Andric 77*0fca6ea1SDimitry Andric /// \returns true if \p MI only defines FPRs. 78*0fca6ea1SDimitry Andric bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 79*0fca6ea1SDimitry Andric const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 80*0fca6ea1SDimitry Andric 815f757f3fSDimitry Andric public: 825f757f3fSDimitry Andric X86RegisterBankInfo(const TargetRegisterInfo &TRI); 835f757f3fSDimitry Andric 845f757f3fSDimitry Andric const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 855f757f3fSDimitry Andric LLT) const override; 865f757f3fSDimitry Andric 875f757f3fSDimitry Andric InstructionMappings 885f757f3fSDimitry Andric getInstrAlternativeMappings(const MachineInstr &MI) const override; 895f757f3fSDimitry Andric 905f757f3fSDimitry Andric /// See RegisterBankInfo::applyMapping. 915f757f3fSDimitry Andric void applyMappingImpl(MachineIRBuilder &Builder, 925f757f3fSDimitry Andric const OperandsMapper &OpdMapper) const override; 935f757f3fSDimitry Andric 945f757f3fSDimitry Andric const InstructionMapping & 955f757f3fSDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 965f757f3fSDimitry Andric }; 975f757f3fSDimitry Andric 985f757f3fSDimitry Andric } // namespace llvm 995f757f3fSDimitry Andric #endif 100