1*0b57cec5SDimitry Andric //===-- WebAssemblyReplacePhysRegs.cpp - Replace phys regs with virt regs -===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric /// 9*0b57cec5SDimitry Andric /// \file 10*0b57cec5SDimitry Andric /// This file implements a pass that replaces physical registers with 11*0b57cec5SDimitry Andric /// virtual registers. 12*0b57cec5SDimitry Andric /// 13*0b57cec5SDimitry Andric /// LLVM expects certain physical registers, such as a stack pointer. However, 14*0b57cec5SDimitry Andric /// WebAssembly doesn't actually have such physical registers. This pass is run 15*0b57cec5SDimitry Andric /// once LLVM no longer needs these registers, and replaces them with virtual 16*0b57cec5SDimitry Andric /// registers, so they can participate in register stackifying and coloring in 17*0b57cec5SDimitry Andric /// the normal way. 18*0b57cec5SDimitry Andric /// 19*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 22*0b57cec5SDimitry Andric #include "WebAssembly.h" 23*0b57cec5SDimitry Andric #include "WebAssemblyMachineFunctionInfo.h" 24*0b57cec5SDimitry Andric #include "WebAssemblySubtarget.h" 25*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h" 26*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 27*0b57cec5SDimitry Andric #include "llvm/CodeGen/Passes.h" 28*0b57cec5SDimitry Andric #include "llvm/Support/Debug.h" 29*0b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h" 30*0b57cec5SDimitry Andric using namespace llvm; 31*0b57cec5SDimitry Andric 32*0b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-replace-phys-regs" 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric namespace { 35*0b57cec5SDimitry Andric class WebAssemblyReplacePhysRegs final : public MachineFunctionPass { 36*0b57cec5SDimitry Andric public: 37*0b57cec5SDimitry Andric static char ID; // Pass identification, replacement for typeid 38*0b57cec5SDimitry Andric WebAssemblyReplacePhysRegs() : MachineFunctionPass(ID) {} 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andric private: 41*0b57cec5SDimitry Andric StringRef getPassName() const override { 42*0b57cec5SDimitry Andric return "WebAssembly Replace Physical Registers"; 43*0b57cec5SDimitry Andric } 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric void getAnalysisUsage(AnalysisUsage &AU) const override { 46*0b57cec5SDimitry Andric AU.setPreservesCFG(); 47*0b57cec5SDimitry Andric MachineFunctionPass::getAnalysisUsage(AU); 48*0b57cec5SDimitry Andric } 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric bool runOnMachineFunction(MachineFunction &MF) override; 51*0b57cec5SDimitry Andric }; 52*0b57cec5SDimitry Andric } // end anonymous namespace 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andric char WebAssemblyReplacePhysRegs::ID = 0; 55*0b57cec5SDimitry Andric INITIALIZE_PASS(WebAssemblyReplacePhysRegs, DEBUG_TYPE, 56*0b57cec5SDimitry Andric "Replace physical registers with virtual registers", false, 57*0b57cec5SDimitry Andric false) 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andric FunctionPass *llvm::createWebAssemblyReplacePhysRegs() { 60*0b57cec5SDimitry Andric return new WebAssemblyReplacePhysRegs(); 61*0b57cec5SDimitry Andric } 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andric bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) { 64*0b57cec5SDimitry Andric LLVM_DEBUG({ 65*0b57cec5SDimitry Andric dbgs() << "********** Replace Physical Registers **********\n" 66*0b57cec5SDimitry Andric << "********** Function: " << MF.getName() << '\n'; 67*0b57cec5SDimitry Andric }); 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric MachineRegisterInfo &MRI = MF.getRegInfo(); 70*0b57cec5SDimitry Andric const auto &TRI = *MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo(); 71*0b57cec5SDimitry Andric bool Changed = false; 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric assert(!mustPreserveAnalysisID(LiveIntervalsID) && 74*0b57cec5SDimitry Andric "LiveIntervals shouldn't be active yet!"); 75*0b57cec5SDimitry Andric // We don't preserve SSA or liveness. 76*0b57cec5SDimitry Andric MRI.leaveSSA(); 77*0b57cec5SDimitry Andric MRI.invalidateLiveness(); 78*0b57cec5SDimitry Andric 79*0b57cec5SDimitry Andric for (unsigned PReg = WebAssembly::NoRegister + 1; 80*0b57cec5SDimitry Andric PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) { 81*0b57cec5SDimitry Andric // Skip fake registers that are never used explicitly. 82*0b57cec5SDimitry Andric if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS) 83*0b57cec5SDimitry Andric continue; 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andric // Replace explicit uses of the physical register with a virtual register. 86*0b57cec5SDimitry Andric const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); 87*0b57cec5SDimitry Andric unsigned VReg = WebAssembly::NoRegister; 88*0b57cec5SDimitry Andric for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E;) { 89*0b57cec5SDimitry Andric MachineOperand &MO = *I++; 90*0b57cec5SDimitry Andric if (!MO.isImplicit()) { 91*0b57cec5SDimitry Andric if (VReg == WebAssembly::NoRegister) 92*0b57cec5SDimitry Andric VReg = MRI.createVirtualRegister(RC); 93*0b57cec5SDimitry Andric MO.setReg(VReg); 94*0b57cec5SDimitry Andric if (MO.getParent()->isDebugValue()) 95*0b57cec5SDimitry Andric MO.setIsDebug(); 96*0b57cec5SDimitry Andric Changed = true; 97*0b57cec5SDimitry Andric } 98*0b57cec5SDimitry Andric } 99*0b57cec5SDimitry Andric } 100*0b57cec5SDimitry Andric 101*0b57cec5SDimitry Andric return Changed; 102*0b57cec5SDimitry Andric } 103