1480093f4SDimitry Andric //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric // 9480093f4SDimitry Andric // This file contains the VE implementation of the TargetInstrInfo class. 10480093f4SDimitry Andric // 11480093f4SDimitry Andric //===----------------------------------------------------------------------===// 12480093f4SDimitry Andric 13480093f4SDimitry Andric #include "VEInstrInfo.h" 14480093f4SDimitry Andric #include "VE.h" 155ffd83dbSDimitry Andric #include "VEMachineFunctionInfo.h" 16480093f4SDimitry Andric #include "VESubtarget.h" 17480093f4SDimitry Andric #include "llvm/ADT/STLExtras.h" 18480093f4SDimitry Andric #include "llvm/ADT/SmallVector.h" 19480093f4SDimitry Andric #include "llvm/CodeGen/MachineFrameInfo.h" 20480093f4SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h" 21480093f4SDimitry Andric #include "llvm/CodeGen/MachineMemOperand.h" 22480093f4SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 23349cc55cSDimitry Andric #include "llvm/MC/TargetRegistry.h" 24480093f4SDimitry Andric #include "llvm/Support/CommandLine.h" 25480093f4SDimitry Andric #include "llvm/Support/Debug.h" 26480093f4SDimitry Andric #include "llvm/Support/ErrorHandling.h" 27480093f4SDimitry Andric 285ffd83dbSDimitry Andric #define DEBUG_TYPE "ve-instr-info" 29480093f4SDimitry Andric 30480093f4SDimitry Andric using namespace llvm; 31480093f4SDimitry Andric 32480093f4SDimitry Andric #define GET_INSTRINFO_CTOR_DTOR 33480093f4SDimitry Andric #include "VEGenInstrInfo.inc" 34480093f4SDimitry Andric 35480093f4SDimitry Andric // Pin the vtable to this file. 36480093f4SDimitry Andric void VEInstrInfo::anchor() {} 37480093f4SDimitry Andric 38480093f4SDimitry Andric VEInstrInfo::VEInstrInfo(VESubtarget &ST) 395ffd83dbSDimitry Andric : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} 405ffd83dbSDimitry Andric 415ffd83dbSDimitry Andric static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); } 425ffd83dbSDimitry Andric 435ffd83dbSDimitry Andric static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) { 445ffd83dbSDimitry Andric switch (CC) { 455ffd83dbSDimitry Andric case VECC::CC_IG: 465ffd83dbSDimitry Andric return VECC::CC_ILE; 475ffd83dbSDimitry Andric case VECC::CC_IL: 485ffd83dbSDimitry Andric return VECC::CC_IGE; 495ffd83dbSDimitry Andric case VECC::CC_INE: 505ffd83dbSDimitry Andric return VECC::CC_IEQ; 515ffd83dbSDimitry Andric case VECC::CC_IEQ: 525ffd83dbSDimitry Andric return VECC::CC_INE; 535ffd83dbSDimitry Andric case VECC::CC_IGE: 545ffd83dbSDimitry Andric return VECC::CC_IL; 555ffd83dbSDimitry Andric case VECC::CC_ILE: 565ffd83dbSDimitry Andric return VECC::CC_IG; 575ffd83dbSDimitry Andric case VECC::CC_AF: 585ffd83dbSDimitry Andric return VECC::CC_AT; 595ffd83dbSDimitry Andric case VECC::CC_G: 605ffd83dbSDimitry Andric return VECC::CC_LENAN; 615ffd83dbSDimitry Andric case VECC::CC_L: 625ffd83dbSDimitry Andric return VECC::CC_GENAN; 635ffd83dbSDimitry Andric case VECC::CC_NE: 645ffd83dbSDimitry Andric return VECC::CC_EQNAN; 655ffd83dbSDimitry Andric case VECC::CC_EQ: 665ffd83dbSDimitry Andric return VECC::CC_NENAN; 675ffd83dbSDimitry Andric case VECC::CC_GE: 685ffd83dbSDimitry Andric return VECC::CC_LNAN; 695ffd83dbSDimitry Andric case VECC::CC_LE: 705ffd83dbSDimitry Andric return VECC::CC_GNAN; 715ffd83dbSDimitry Andric case VECC::CC_NUM: 725ffd83dbSDimitry Andric return VECC::CC_NAN; 735ffd83dbSDimitry Andric case VECC::CC_NAN: 745ffd83dbSDimitry Andric return VECC::CC_NUM; 755ffd83dbSDimitry Andric case VECC::CC_GNAN: 765ffd83dbSDimitry Andric return VECC::CC_LE; 775ffd83dbSDimitry Andric case VECC::CC_LNAN: 785ffd83dbSDimitry Andric return VECC::CC_GE; 795ffd83dbSDimitry Andric case VECC::CC_NENAN: 805ffd83dbSDimitry Andric return VECC::CC_EQ; 815ffd83dbSDimitry Andric case VECC::CC_EQNAN: 825ffd83dbSDimitry Andric return VECC::CC_NE; 835ffd83dbSDimitry Andric case VECC::CC_GENAN: 845ffd83dbSDimitry Andric return VECC::CC_L; 855ffd83dbSDimitry Andric case VECC::CC_LENAN: 865ffd83dbSDimitry Andric return VECC::CC_G; 875ffd83dbSDimitry Andric case VECC::CC_AT: 885ffd83dbSDimitry Andric return VECC::CC_AF; 895ffd83dbSDimitry Andric case VECC::UNKNOWN: 905ffd83dbSDimitry Andric return VECC::UNKNOWN; 915ffd83dbSDimitry Andric } 925ffd83dbSDimitry Andric llvm_unreachable("Invalid cond code"); 935ffd83dbSDimitry Andric } 945ffd83dbSDimitry Andric 95e8d8bef9SDimitry Andric // Treat a branch relative long always instruction as unconditional branch. 96e8d8bef9SDimitry Andric // For example, br.l.t and br.l. 975ffd83dbSDimitry Andric static bool isUncondBranchOpcode(int Opc) { 98e8d8bef9SDimitry Andric using namespace llvm::VE; 99e8d8bef9SDimitry Andric 100e8d8bef9SDimitry Andric #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t) 101e8d8bef9SDimitry Andric // VE has other branch relative always instructions for word/double/float, 102349cc55cSDimitry Andric // but we use only long branches in our lower. So, check it here. 103e8d8bef9SDimitry Andric assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) && 104e8d8bef9SDimitry Andric "Branch relative word/double/float always instructions should not be " 105e8d8bef9SDimitry Andric "used!"); 106e8d8bef9SDimitry Andric return BRKIND(BRCFL); 107e8d8bef9SDimitry Andric #undef BRKIND 1085ffd83dbSDimitry Andric } 1095ffd83dbSDimitry Andric 110e8d8bef9SDimitry Andric // Treat branch relative conditional as conditional branch instructions. 111e8d8bef9SDimitry Andric // For example, brgt.l.t and brle.s.nt. 1125ffd83dbSDimitry Andric static bool isCondBranchOpcode(int Opc) { 113e8d8bef9SDimitry Andric using namespace llvm::VE; 114e8d8bef9SDimitry Andric 115e8d8bef9SDimitry Andric #define BRKIND(NAME) \ 116e8d8bef9SDimitry Andric (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \ 117e8d8bef9SDimitry Andric Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t) 118e8d8bef9SDimitry Andric return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS); 119e8d8bef9SDimitry Andric #undef BRKIND 1205ffd83dbSDimitry Andric } 1215ffd83dbSDimitry Andric 122e8d8bef9SDimitry Andric // Treat branch long always instructions as indirect branch. 123e8d8bef9SDimitry Andric // For example, b.l.t and b.l. 1245ffd83dbSDimitry Andric static bool isIndirectBranchOpcode(int Opc) { 125e8d8bef9SDimitry Andric using namespace llvm::VE; 126e8d8bef9SDimitry Andric 127e8d8bef9SDimitry Andric #define BRKIND(NAME) \ 128e8d8bef9SDimitry Andric (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t) 129e8d8bef9SDimitry Andric // VE has other branch always instructions for word/double/float, but 130349cc55cSDimitry Andric // we use only long branches in our lower. So, check it here. 131e8d8bef9SDimitry Andric assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) && 132e8d8bef9SDimitry Andric "Branch word/double/float always instructions should not be used!"); 133e8d8bef9SDimitry Andric return BRKIND(BCFL); 134e8d8bef9SDimitry Andric #undef BRKIND 1355ffd83dbSDimitry Andric } 1365ffd83dbSDimitry Andric 1375ffd83dbSDimitry Andric static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, 1385ffd83dbSDimitry Andric SmallVectorImpl<MachineOperand> &Cond) { 1395ffd83dbSDimitry Andric Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); 1405ffd83dbSDimitry Andric Cond.push_back(LastInst->getOperand(1)); 1415ffd83dbSDimitry Andric Cond.push_back(LastInst->getOperand(2)); 1425ffd83dbSDimitry Andric Target = LastInst->getOperand(3).getMBB(); 1435ffd83dbSDimitry Andric } 1445ffd83dbSDimitry Andric 1455ffd83dbSDimitry Andric bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 1465ffd83dbSDimitry Andric MachineBasicBlock *&FBB, 1475ffd83dbSDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 1485ffd83dbSDimitry Andric bool AllowModify) const { 1495ffd83dbSDimitry Andric MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 1505ffd83dbSDimitry Andric if (I == MBB.end()) 1515ffd83dbSDimitry Andric return false; 1525ffd83dbSDimitry Andric 1535ffd83dbSDimitry Andric if (!isUnpredicatedTerminator(*I)) 1545ffd83dbSDimitry Andric return false; 1555ffd83dbSDimitry Andric 1565ffd83dbSDimitry Andric // Get the last instruction in the block. 1575ffd83dbSDimitry Andric MachineInstr *LastInst = &*I; 1585ffd83dbSDimitry Andric unsigned LastOpc = LastInst->getOpcode(); 1595ffd83dbSDimitry Andric 1605ffd83dbSDimitry Andric // If there is only one terminator instruction, process it. 1615ffd83dbSDimitry Andric if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 1625ffd83dbSDimitry Andric if (isUncondBranchOpcode(LastOpc)) { 1635ffd83dbSDimitry Andric TBB = LastInst->getOperand(0).getMBB(); 1645ffd83dbSDimitry Andric return false; 1655ffd83dbSDimitry Andric } 1665ffd83dbSDimitry Andric if (isCondBranchOpcode(LastOpc)) { 1675ffd83dbSDimitry Andric // Block ends with fall-through condbranch. 1685ffd83dbSDimitry Andric parseCondBranch(LastInst, TBB, Cond); 1695ffd83dbSDimitry Andric return false; 1705ffd83dbSDimitry Andric } 1715ffd83dbSDimitry Andric return true; // Can't handle indirect branch. 1725ffd83dbSDimitry Andric } 1735ffd83dbSDimitry Andric 1745ffd83dbSDimitry Andric // Get the instruction before it if it is a terminator. 1755ffd83dbSDimitry Andric MachineInstr *SecondLastInst = &*I; 1765ffd83dbSDimitry Andric unsigned SecondLastOpc = SecondLastInst->getOpcode(); 1775ffd83dbSDimitry Andric 1785ffd83dbSDimitry Andric // If AllowModify is true and the block ends with two or more unconditional 1795ffd83dbSDimitry Andric // branches, delete all but the first unconditional branch. 1805ffd83dbSDimitry Andric if (AllowModify && isUncondBranchOpcode(LastOpc)) { 1815ffd83dbSDimitry Andric while (isUncondBranchOpcode(SecondLastOpc)) { 1825ffd83dbSDimitry Andric LastInst->eraseFromParent(); 1835ffd83dbSDimitry Andric LastInst = SecondLastInst; 1845ffd83dbSDimitry Andric LastOpc = LastInst->getOpcode(); 1855ffd83dbSDimitry Andric if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 1865ffd83dbSDimitry Andric // Return now the only terminator is an unconditional branch. 1875ffd83dbSDimitry Andric TBB = LastInst->getOperand(0).getMBB(); 1885ffd83dbSDimitry Andric return false; 1895ffd83dbSDimitry Andric } 1905ffd83dbSDimitry Andric SecondLastInst = &*I; 1915ffd83dbSDimitry Andric SecondLastOpc = SecondLastInst->getOpcode(); 1925ffd83dbSDimitry Andric } 1935ffd83dbSDimitry Andric } 1945ffd83dbSDimitry Andric 1955ffd83dbSDimitry Andric // If there are three terminators, we don't know what sort of block this is. 1965ffd83dbSDimitry Andric if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 1975ffd83dbSDimitry Andric return true; 1985ffd83dbSDimitry Andric 1995ffd83dbSDimitry Andric // If the block ends with a B and a Bcc, handle it. 2005ffd83dbSDimitry Andric if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 2015ffd83dbSDimitry Andric parseCondBranch(SecondLastInst, TBB, Cond); 2025ffd83dbSDimitry Andric FBB = LastInst->getOperand(0).getMBB(); 2035ffd83dbSDimitry Andric return false; 2045ffd83dbSDimitry Andric } 2055ffd83dbSDimitry Andric 2065ffd83dbSDimitry Andric // If the block ends with two unconditional branches, handle it. The second 2075ffd83dbSDimitry Andric // one is not executed. 2085ffd83dbSDimitry Andric if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 2095ffd83dbSDimitry Andric TBB = SecondLastInst->getOperand(0).getMBB(); 2105ffd83dbSDimitry Andric return false; 2115ffd83dbSDimitry Andric } 2125ffd83dbSDimitry Andric 2135ffd83dbSDimitry Andric // ...likewise if it ends with an indirect branch followed by an unconditional 2145ffd83dbSDimitry Andric // branch. 2155ffd83dbSDimitry Andric if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 2165ffd83dbSDimitry Andric I = LastInst; 2175ffd83dbSDimitry Andric if (AllowModify) 2185ffd83dbSDimitry Andric I->eraseFromParent(); 2195ffd83dbSDimitry Andric return true; 2205ffd83dbSDimitry Andric } 2215ffd83dbSDimitry Andric 2225ffd83dbSDimitry Andric // Otherwise, can't handle this. 2235ffd83dbSDimitry Andric return true; 2245ffd83dbSDimitry Andric } 2255ffd83dbSDimitry Andric 2265ffd83dbSDimitry Andric unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, 2275ffd83dbSDimitry Andric MachineBasicBlock *TBB, 2285ffd83dbSDimitry Andric MachineBasicBlock *FBB, 2295ffd83dbSDimitry Andric ArrayRef<MachineOperand> Cond, 2305ffd83dbSDimitry Andric const DebugLoc &DL, int *BytesAdded) const { 2315ffd83dbSDimitry Andric assert(TBB && "insertBranch must not be told to insert a fallthrough"); 2325ffd83dbSDimitry Andric assert((Cond.size() == 3 || Cond.size() == 0) && 2335ffd83dbSDimitry Andric "VE branch conditions should have three component!"); 2345ffd83dbSDimitry Andric assert(!BytesAdded && "code size not handled"); 2355ffd83dbSDimitry Andric if (Cond.empty()) { 2365ffd83dbSDimitry Andric // Uncondition branch 2375ffd83dbSDimitry Andric assert(!FBB && "Unconditional branch with multiple successors!"); 2385ffd83dbSDimitry Andric BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 2395ffd83dbSDimitry Andric .addMBB(TBB); 2405ffd83dbSDimitry Andric return 1; 2415ffd83dbSDimitry Andric } 2425ffd83dbSDimitry Andric 2435ffd83dbSDimitry Andric // Conditional branch 2445ffd83dbSDimitry Andric // (BRCFir CC sy sz addr) 2455ffd83dbSDimitry Andric assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); 2465ffd83dbSDimitry Andric 2475ffd83dbSDimitry Andric unsigned opc[2]; 2485ffd83dbSDimitry Andric const TargetRegisterInfo *TRI = &getRegisterInfo(); 2495ffd83dbSDimitry Andric MachineFunction *MF = MBB.getParent(); 2505ffd83dbSDimitry Andric const MachineRegisterInfo &MRI = MF->getRegInfo(); 25104eeddc0SDimitry Andric Register Reg = Cond[2].getReg(); 2525ffd83dbSDimitry Andric if (IsIntegerCC(Cond[0].getImm())) { 2535ffd83dbSDimitry Andric if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 2545ffd83dbSDimitry Andric opc[0] = VE::BRCFWir; 2555ffd83dbSDimitry Andric opc[1] = VE::BRCFWrr; 2565ffd83dbSDimitry Andric } else { 2575ffd83dbSDimitry Andric opc[0] = VE::BRCFLir; 2585ffd83dbSDimitry Andric opc[1] = VE::BRCFLrr; 2595ffd83dbSDimitry Andric } 2605ffd83dbSDimitry Andric } else { 2615ffd83dbSDimitry Andric if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 2625ffd83dbSDimitry Andric opc[0] = VE::BRCFSir; 2635ffd83dbSDimitry Andric opc[1] = VE::BRCFSrr; 2645ffd83dbSDimitry Andric } else { 2655ffd83dbSDimitry Andric opc[0] = VE::BRCFDir; 2665ffd83dbSDimitry Andric opc[1] = VE::BRCFDrr; 2675ffd83dbSDimitry Andric } 2685ffd83dbSDimitry Andric } 2695ffd83dbSDimitry Andric if (Cond[1].isImm()) { 2705ffd83dbSDimitry Andric BuildMI(&MBB, DL, get(opc[0])) 2715ffd83dbSDimitry Andric .add(Cond[0]) // condition code 2725ffd83dbSDimitry Andric .add(Cond[1]) // lhs 2735ffd83dbSDimitry Andric .add(Cond[2]) // rhs 2745ffd83dbSDimitry Andric .addMBB(TBB); 2755ffd83dbSDimitry Andric } else { 2765ffd83dbSDimitry Andric BuildMI(&MBB, DL, get(opc[1])) 2775ffd83dbSDimitry Andric .add(Cond[0]) 2785ffd83dbSDimitry Andric .add(Cond[1]) 2795ffd83dbSDimitry Andric .add(Cond[2]) 2805ffd83dbSDimitry Andric .addMBB(TBB); 2815ffd83dbSDimitry Andric } 2825ffd83dbSDimitry Andric 2835ffd83dbSDimitry Andric if (!FBB) 2845ffd83dbSDimitry Andric return 1; 2855ffd83dbSDimitry Andric 2865ffd83dbSDimitry Andric BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 2875ffd83dbSDimitry Andric .addMBB(FBB); 2885ffd83dbSDimitry Andric return 2; 2895ffd83dbSDimitry Andric } 2905ffd83dbSDimitry Andric 2915ffd83dbSDimitry Andric unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, 2925ffd83dbSDimitry Andric int *BytesRemoved) const { 2935ffd83dbSDimitry Andric assert(!BytesRemoved && "code size not handled"); 2945ffd83dbSDimitry Andric 2955ffd83dbSDimitry Andric MachineBasicBlock::iterator I = MBB.end(); 2965ffd83dbSDimitry Andric unsigned Count = 0; 2975ffd83dbSDimitry Andric while (I != MBB.begin()) { 2985ffd83dbSDimitry Andric --I; 2995ffd83dbSDimitry Andric 3005ffd83dbSDimitry Andric if (I->isDebugValue()) 3015ffd83dbSDimitry Andric continue; 3025ffd83dbSDimitry Andric 3035ffd83dbSDimitry Andric if (!isUncondBranchOpcode(I->getOpcode()) && 3045ffd83dbSDimitry Andric !isCondBranchOpcode(I->getOpcode())) 3055ffd83dbSDimitry Andric break; // Not a branch 3065ffd83dbSDimitry Andric 3075ffd83dbSDimitry Andric I->eraseFromParent(); 3085ffd83dbSDimitry Andric I = MBB.end(); 3095ffd83dbSDimitry Andric ++Count; 3105ffd83dbSDimitry Andric } 3115ffd83dbSDimitry Andric return Count; 3125ffd83dbSDimitry Andric } 3135ffd83dbSDimitry Andric 3145ffd83dbSDimitry Andric bool VEInstrInfo::reverseBranchCondition( 3155ffd83dbSDimitry Andric SmallVectorImpl<MachineOperand> &Cond) const { 3165ffd83dbSDimitry Andric VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm()); 3175ffd83dbSDimitry Andric Cond[0].setImm(GetOppositeBranchCondition(CC)); 3185ffd83dbSDimitry Andric return false; 3195ffd83dbSDimitry Andric } 3205ffd83dbSDimitry Andric 3215ffd83dbSDimitry Andric static bool IsAliasOfSX(Register Reg) { 322e8d8bef9SDimitry Andric return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || 3235ffd83dbSDimitry Andric VE::F32RegClass.contains(Reg); 3245ffd83dbSDimitry Andric } 3255ffd83dbSDimitry Andric 326e8d8bef9SDimitry Andric static void copyPhysSubRegs(MachineBasicBlock &MBB, 327e8d8bef9SDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL, 328e8d8bef9SDimitry Andric MCRegister DestReg, MCRegister SrcReg, bool KillSrc, 329e8d8bef9SDimitry Andric const MCInstrDesc &MCID, unsigned int NumSubRegs, 330e8d8bef9SDimitry Andric const unsigned *SubRegIdx, 331e8d8bef9SDimitry Andric const TargetRegisterInfo *TRI) { 332e8d8bef9SDimitry Andric MachineInstr *MovMI = nullptr; 333e8d8bef9SDimitry Andric 334e8d8bef9SDimitry Andric for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { 335e8d8bef9SDimitry Andric Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); 336e8d8bef9SDimitry Andric Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); 337e8d8bef9SDimitry Andric assert(SubDest && SubSrc && "Bad sub-register"); 338e8d8bef9SDimitry Andric 339e8d8bef9SDimitry Andric if (MCID.getOpcode() == VE::ORri) { 340e8d8bef9SDimitry Andric // generate "ORri, dest, src, 0" instruction. 341e8d8bef9SDimitry Andric MachineInstrBuilder MIB = 342e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); 343e8d8bef9SDimitry Andric MovMI = MIB.getInstr(); 344e8d8bef9SDimitry Andric } else if (MCID.getOpcode() == VE::ANDMmm) { 345e8d8bef9SDimitry Andric // generate "ANDM, dest, vm0, src" instruction. 346e8d8bef9SDimitry Andric MachineInstrBuilder MIB = 347e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); 348e8d8bef9SDimitry Andric MovMI = MIB.getInstr(); 349e8d8bef9SDimitry Andric } else { 350e8d8bef9SDimitry Andric llvm_unreachable("Unexpected reg-to-reg copy instruction"); 351e8d8bef9SDimitry Andric } 352e8d8bef9SDimitry Andric } 353e8d8bef9SDimitry Andric // Add implicit super-register defs and kills to the last MovMI. 354e8d8bef9SDimitry Andric MovMI->addRegisterDefined(DestReg, TRI); 355e8d8bef9SDimitry Andric if (KillSrc) 356e8d8bef9SDimitry Andric MovMI->addRegisterKilled(SrcReg, TRI, true); 357e8d8bef9SDimitry Andric } 358e8d8bef9SDimitry Andric 3595ffd83dbSDimitry Andric void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 3605ffd83dbSDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL, 3615ffd83dbSDimitry Andric MCRegister DestReg, MCRegister SrcReg, 3625ffd83dbSDimitry Andric bool KillSrc) const { 3635ffd83dbSDimitry Andric 3645ffd83dbSDimitry Andric if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { 3655ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::ORri), DestReg) 3665ffd83dbSDimitry Andric .addReg(SrcReg, getKillRegState(KillSrc)) 3675ffd83dbSDimitry Andric .addImm(0); 368e8d8bef9SDimitry Andric } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { 369e8d8bef9SDimitry Andric // Generate following instructions 370e8d8bef9SDimitry Andric // %sw16 = LEA32zii 256 371e8d8bef9SDimitry Andric // VORmvl %dest, (0)1, %src, %sw16 372e8d8bef9SDimitry Andric // TODO: reuse a register if vl is already assigned to a register 373e8d8bef9SDimitry Andric // FIXME: it would be better to scavenge a register here instead of 374e8d8bef9SDimitry Andric // reserving SX16 all of the time. 375e8d8bef9SDimitry Andric const TargetRegisterInfo *TRI = &getRegisterInfo(); 376e8d8bef9SDimitry Andric Register TmpReg = VE::SX16; 377e8d8bef9SDimitry Andric Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); 378e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) 379e8d8bef9SDimitry Andric .addImm(0) 380e8d8bef9SDimitry Andric .addImm(0) 381e8d8bef9SDimitry Andric .addImm(256); 382e8d8bef9SDimitry Andric MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) 383e8d8bef9SDimitry Andric .addImm(M1(0)) // Represent (0)1. 384e8d8bef9SDimitry Andric .addReg(SrcReg, getKillRegState(KillSrc)) 385e8d8bef9SDimitry Andric .addReg(SubTmp, getKillRegState(true)); 386e8d8bef9SDimitry Andric MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); 387e8d8bef9SDimitry Andric } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { 388e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) 389e8d8bef9SDimitry Andric .addReg(VE::VM0) 390e8d8bef9SDimitry Andric .addReg(SrcReg, getKillRegState(KillSrc)); 391e8d8bef9SDimitry Andric } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) { 392e8d8bef9SDimitry Andric // Use two instructions. 393e8d8bef9SDimitry Andric const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; 394e8d8bef9SDimitry Andric unsigned int NumSubRegs = 2; 395e8d8bef9SDimitry Andric copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm), 396e8d8bef9SDimitry Andric NumSubRegs, SubRegIdx, &getRegisterInfo()); 397e8d8bef9SDimitry Andric } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { 398e8d8bef9SDimitry Andric // Use two instructions. 399e8d8bef9SDimitry Andric const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; 400e8d8bef9SDimitry Andric unsigned int NumSubRegs = 2; 401e8d8bef9SDimitry Andric copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), 402e8d8bef9SDimitry Andric NumSubRegs, SubRegIdx, &getRegisterInfo()); 4035ffd83dbSDimitry Andric } else { 4045ffd83dbSDimitry Andric const TargetRegisterInfo *TRI = &getRegisterInfo(); 4055ffd83dbSDimitry Andric dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI) 4065ffd83dbSDimitry Andric << " to " << printReg(DestReg, TRI) << "\n"; 4075ffd83dbSDimitry Andric llvm_unreachable("Impossible reg-to-reg copy"); 4085ffd83dbSDimitry Andric } 4095ffd83dbSDimitry Andric } 4105ffd83dbSDimitry Andric 4115ffd83dbSDimitry Andric /// isLoadFromStackSlot - If the specified machine instruction is a direct 4125ffd83dbSDimitry Andric /// load from a stack slot, return the virtual or physical register number of 4135ffd83dbSDimitry Andric /// the destination along with the FrameIndex of the loaded stack slot. If 4145ffd83dbSDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 4155ffd83dbSDimitry Andric /// any side effects other than loading from the stack slot. 416*0fca6ea1SDimitry Andric Register VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 4175ffd83dbSDimitry Andric int &FrameIndex) const { 4185ffd83dbSDimitry Andric if (MI.getOpcode() == VE::LDrii || // I64 4195ffd83dbSDimitry Andric MI.getOpcode() == VE::LDLSXrii || // I32 420e8d8bef9SDimitry Andric MI.getOpcode() == VE::LDUrii || // F32 421fcaf7f86SDimitry Andric MI.getOpcode() == VE::LDQrii || // F128 (pseudo) 422fcaf7f86SDimitry Andric MI.getOpcode() == VE::LDVMrii || // VM (pseudo) 423fcaf7f86SDimitry Andric MI.getOpcode() == VE::LDVM512rii // VM512 (pseudo) 4245ffd83dbSDimitry Andric ) { 4255ffd83dbSDimitry Andric if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 4265ffd83dbSDimitry Andric MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() && 4275ffd83dbSDimitry Andric MI.getOperand(3).getImm() == 0) { 4285ffd83dbSDimitry Andric FrameIndex = MI.getOperand(1).getIndex(); 4295ffd83dbSDimitry Andric return MI.getOperand(0).getReg(); 4305ffd83dbSDimitry Andric } 4315ffd83dbSDimitry Andric } 4325ffd83dbSDimitry Andric return 0; 4335ffd83dbSDimitry Andric } 4345ffd83dbSDimitry Andric 4355ffd83dbSDimitry Andric /// isStoreToStackSlot - If the specified machine instruction is a direct 4365ffd83dbSDimitry Andric /// store to a stack slot, return the virtual or physical register number of 4375ffd83dbSDimitry Andric /// the source reg along with the FrameIndex of the loaded stack slot. If 4385ffd83dbSDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 4395ffd83dbSDimitry Andric /// any side effects other than storing to the stack slot. 440*0fca6ea1SDimitry Andric Register VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 4415ffd83dbSDimitry Andric int &FrameIndex) const { 4425ffd83dbSDimitry Andric if (MI.getOpcode() == VE::STrii || // I64 4435ffd83dbSDimitry Andric MI.getOpcode() == VE::STLrii || // I32 444e8d8bef9SDimitry Andric MI.getOpcode() == VE::STUrii || // F32 445fcaf7f86SDimitry Andric MI.getOpcode() == VE::STQrii || // F128 (pseudo) 446fcaf7f86SDimitry Andric MI.getOpcode() == VE::STVMrii || // VM (pseudo) 447fcaf7f86SDimitry Andric MI.getOpcode() == VE::STVM512rii // VM512 (pseudo) 4485ffd83dbSDimitry Andric ) { 4495ffd83dbSDimitry Andric if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && 4505ffd83dbSDimitry Andric MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() && 4515ffd83dbSDimitry Andric MI.getOperand(2).getImm() == 0) { 4525ffd83dbSDimitry Andric FrameIndex = MI.getOperand(0).getIndex(); 4535ffd83dbSDimitry Andric return MI.getOperand(3).getReg(); 4545ffd83dbSDimitry Andric } 4555ffd83dbSDimitry Andric } 4565ffd83dbSDimitry Andric return 0; 4575ffd83dbSDimitry Andric } 4585ffd83dbSDimitry Andric 4595ffd83dbSDimitry Andric void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 4605ffd83dbSDimitry Andric MachineBasicBlock::iterator I, 4615ffd83dbSDimitry Andric Register SrcReg, bool isKill, int FI, 4625ffd83dbSDimitry Andric const TargetRegisterClass *RC, 463bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 464bdd1243dSDimitry Andric Register VReg) const { 4655ffd83dbSDimitry Andric DebugLoc DL; 4665ffd83dbSDimitry Andric if (I != MBB.end()) 4675ffd83dbSDimitry Andric DL = I->getDebugLoc(); 4685ffd83dbSDimitry Andric 4695ffd83dbSDimitry Andric MachineFunction *MF = MBB.getParent(); 4705ffd83dbSDimitry Andric const MachineFrameInfo &MFI = MF->getFrameInfo(); 4715ffd83dbSDimitry Andric MachineMemOperand *MMO = MF->getMachineMemOperand( 4725ffd83dbSDimitry Andric MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 4735ffd83dbSDimitry Andric MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 4745ffd83dbSDimitry Andric 4755ffd83dbSDimitry Andric // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 4765ffd83dbSDimitry Andric if (RC == &VE::I64RegClass) { 4775ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::STrii)) 4785ffd83dbSDimitry Andric .addFrameIndex(FI) 4795ffd83dbSDimitry Andric .addImm(0) 4805ffd83dbSDimitry Andric .addImm(0) 4815ffd83dbSDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 4825ffd83dbSDimitry Andric .addMemOperand(MMO); 4835ffd83dbSDimitry Andric } else if (RC == &VE::I32RegClass) { 4845ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::STLrii)) 4855ffd83dbSDimitry Andric .addFrameIndex(FI) 4865ffd83dbSDimitry Andric .addImm(0) 4875ffd83dbSDimitry Andric .addImm(0) 4885ffd83dbSDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 4895ffd83dbSDimitry Andric .addMemOperand(MMO); 4905ffd83dbSDimitry Andric } else if (RC == &VE::F32RegClass) { 4915ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::STUrii)) 4925ffd83dbSDimitry Andric .addFrameIndex(FI) 4935ffd83dbSDimitry Andric .addImm(0) 4945ffd83dbSDimitry Andric .addImm(0) 4955ffd83dbSDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 4965ffd83dbSDimitry Andric .addMemOperand(MMO); 497e8d8bef9SDimitry Andric } else if (VE::F128RegClass.hasSubClassEq(RC)) { 498e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, get(VE::STQrii)) 499e8d8bef9SDimitry Andric .addFrameIndex(FI) 500e8d8bef9SDimitry Andric .addImm(0) 501e8d8bef9SDimitry Andric .addImm(0) 502e8d8bef9SDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 503e8d8bef9SDimitry Andric .addMemOperand(MMO); 504fcaf7f86SDimitry Andric } else if (RC == &VE::VMRegClass) { 505fcaf7f86SDimitry Andric BuildMI(MBB, I, DL, get(VE::STVMrii)) 506fcaf7f86SDimitry Andric .addFrameIndex(FI) 507fcaf7f86SDimitry Andric .addImm(0) 508fcaf7f86SDimitry Andric .addImm(0) 509fcaf7f86SDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 510fcaf7f86SDimitry Andric .addMemOperand(MMO); 511fcaf7f86SDimitry Andric } else if (VE::VM512RegClass.hasSubClassEq(RC)) { 512fcaf7f86SDimitry Andric BuildMI(MBB, I, DL, get(VE::STVM512rii)) 513fcaf7f86SDimitry Andric .addFrameIndex(FI) 514fcaf7f86SDimitry Andric .addImm(0) 515fcaf7f86SDimitry Andric .addImm(0) 516fcaf7f86SDimitry Andric .addReg(SrcReg, getKillRegState(isKill)) 517fcaf7f86SDimitry Andric .addMemOperand(MMO); 5185ffd83dbSDimitry Andric } else 5195ffd83dbSDimitry Andric report_fatal_error("Can't store this register to stack slot"); 5205ffd83dbSDimitry Andric } 5215ffd83dbSDimitry Andric 5225ffd83dbSDimitry Andric void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 5235ffd83dbSDimitry Andric MachineBasicBlock::iterator I, 5245ffd83dbSDimitry Andric Register DestReg, int FI, 5255ffd83dbSDimitry Andric const TargetRegisterClass *RC, 526bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 527bdd1243dSDimitry Andric Register VReg) const { 5285ffd83dbSDimitry Andric DebugLoc DL; 5295ffd83dbSDimitry Andric if (I != MBB.end()) 5305ffd83dbSDimitry Andric DL = I->getDebugLoc(); 5315ffd83dbSDimitry Andric 5325ffd83dbSDimitry Andric MachineFunction *MF = MBB.getParent(); 5335ffd83dbSDimitry Andric const MachineFrameInfo &MFI = MF->getFrameInfo(); 5345ffd83dbSDimitry Andric MachineMemOperand *MMO = MF->getMachineMemOperand( 5355ffd83dbSDimitry Andric MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 5365ffd83dbSDimitry Andric MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 5375ffd83dbSDimitry Andric 5385ffd83dbSDimitry Andric if (RC == &VE::I64RegClass) { 5395ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) 5405ffd83dbSDimitry Andric .addFrameIndex(FI) 5415ffd83dbSDimitry Andric .addImm(0) 5425ffd83dbSDimitry Andric .addImm(0) 5435ffd83dbSDimitry Andric .addMemOperand(MMO); 5445ffd83dbSDimitry Andric } else if (RC == &VE::I32RegClass) { 5455ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) 5465ffd83dbSDimitry Andric .addFrameIndex(FI) 5475ffd83dbSDimitry Andric .addImm(0) 5485ffd83dbSDimitry Andric .addImm(0) 5495ffd83dbSDimitry Andric .addMemOperand(MMO); 5505ffd83dbSDimitry Andric } else if (RC == &VE::F32RegClass) { 5515ffd83dbSDimitry Andric BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) 5525ffd83dbSDimitry Andric .addFrameIndex(FI) 5535ffd83dbSDimitry Andric .addImm(0) 5545ffd83dbSDimitry Andric .addImm(0) 5555ffd83dbSDimitry Andric .addMemOperand(MMO); 556e8d8bef9SDimitry Andric } else if (VE::F128RegClass.hasSubClassEq(RC)) { 557e8d8bef9SDimitry Andric BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) 558e8d8bef9SDimitry Andric .addFrameIndex(FI) 559e8d8bef9SDimitry Andric .addImm(0) 560e8d8bef9SDimitry Andric .addImm(0) 561e8d8bef9SDimitry Andric .addMemOperand(MMO); 562fcaf7f86SDimitry Andric } else if (RC == &VE::VMRegClass) { 563fcaf7f86SDimitry Andric BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg) 564fcaf7f86SDimitry Andric .addFrameIndex(FI) 565fcaf7f86SDimitry Andric .addImm(0) 566fcaf7f86SDimitry Andric .addImm(0) 567fcaf7f86SDimitry Andric .addMemOperand(MMO); 568fcaf7f86SDimitry Andric } else if (VE::VM512RegClass.hasSubClassEq(RC)) { 569fcaf7f86SDimitry Andric BuildMI(MBB, I, DL, get(VE::LDVM512rii), DestReg) 570fcaf7f86SDimitry Andric .addFrameIndex(FI) 571fcaf7f86SDimitry Andric .addImm(0) 572fcaf7f86SDimitry Andric .addImm(0) 573fcaf7f86SDimitry Andric .addMemOperand(MMO); 5745ffd83dbSDimitry Andric } else 5755ffd83dbSDimitry Andric report_fatal_error("Can't load this register from stack slot"); 5765ffd83dbSDimitry Andric } 5775ffd83dbSDimitry Andric 578*0fca6ea1SDimitry Andric bool VEInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 579e8d8bef9SDimitry Andric Register Reg, MachineRegisterInfo *MRI) const { 580*0fca6ea1SDimitry Andric LLVM_DEBUG(dbgs() << "foldImmediate\n"); 581e8d8bef9SDimitry Andric 582e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "checking DefMI\n"); 583e8d8bef9SDimitry Andric int64_t ImmVal; 584e8d8bef9SDimitry Andric switch (DefMI.getOpcode()) { 585e8d8bef9SDimitry Andric default: 586e8d8bef9SDimitry Andric return false; 587e8d8bef9SDimitry Andric case VE::ORim: 588e8d8bef9SDimitry Andric // General move small immediate instruction on VE. 589e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "checking ORim\n"); 590e8d8bef9SDimitry Andric LLVM_DEBUG(DefMI.dump()); 591e8d8bef9SDimitry Andric // FIXME: We may need to support FPImm too. 592e8d8bef9SDimitry Andric assert(DefMI.getOperand(1).isImm()); 593e8d8bef9SDimitry Andric assert(DefMI.getOperand(2).isImm()); 594e8d8bef9SDimitry Andric ImmVal = 595e8d8bef9SDimitry Andric DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); 596e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 597e8d8bef9SDimitry Andric break; 598e8d8bef9SDimitry Andric case VE::LEAzii: 599e8d8bef9SDimitry Andric // General move immediate instruction on VE. 600e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "checking LEAzii\n"); 601e8d8bef9SDimitry Andric LLVM_DEBUG(DefMI.dump()); 602e8d8bef9SDimitry Andric // FIXME: We may need to support FPImm too. 603e8d8bef9SDimitry Andric assert(DefMI.getOperand(2).isImm()); 604e8d8bef9SDimitry Andric if (!DefMI.getOperand(3).isImm()) 605e8d8bef9SDimitry Andric // LEAzii may refer label 606e8d8bef9SDimitry Andric return false; 607e8d8bef9SDimitry Andric ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); 608e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 609e8d8bef9SDimitry Andric break; 610e8d8bef9SDimitry Andric } 611e8d8bef9SDimitry Andric 612e8d8bef9SDimitry Andric // Try to fold like below: 613e8d8bef9SDimitry Andric // %1:i64 = ORim 0, 0(1) 614e8d8bef9SDimitry Andric // %2:i64 = CMPSLrr %0, %1 615e8d8bef9SDimitry Andric // To 616e8d8bef9SDimitry Andric // %2:i64 = CMPSLrm %0, 0(1) 617e8d8bef9SDimitry Andric // 618e8d8bef9SDimitry Andric // Another example: 619e8d8bef9SDimitry Andric // %1:i64 = ORim 6, 0(1) 620e8d8bef9SDimitry Andric // %2:i64 = CMPSLrr %1, %0 621e8d8bef9SDimitry Andric // To 622e8d8bef9SDimitry Andric // %2:i64 = CMPSLir 6, %0 623e8d8bef9SDimitry Andric // 624e8d8bef9SDimitry Andric // Support commutable instructions like below: 625e8d8bef9SDimitry Andric // %1:i64 = ORim 6, 0(1) 626e8d8bef9SDimitry Andric // %2:i64 = ADDSLrr %1, %0 627e8d8bef9SDimitry Andric // To 628e8d8bef9SDimitry Andric // %2:i64 = ADDSLri %0, 6 629e8d8bef9SDimitry Andric // 630e8d8bef9SDimitry Andric // FIXME: Need to support i32. Current implementtation requires 631e8d8bef9SDimitry Andric // EXTRACT_SUBREG, so input has following COPY and it avoids folding: 632e8d8bef9SDimitry Andric // %1:i64 = ORim 6, 0(1) 633e8d8bef9SDimitry Andric // %2:i32 = COPY %1.sub_i32 634e8d8bef9SDimitry Andric // %3:i32 = ADDSWSXrr %0, %2 635e8d8bef9SDimitry Andric // FIXME: Need to support shift, cmov, and more instructions. 636e8d8bef9SDimitry Andric // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt. 637e8d8bef9SDimitry Andric 638e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "checking UseMI\n"); 639e8d8bef9SDimitry Andric LLVM_DEBUG(UseMI.dump()); 640e8d8bef9SDimitry Andric unsigned NewUseOpcSImm7; 641e8d8bef9SDimitry Andric unsigned NewUseOpcMImm; 642e8d8bef9SDimitry Andric enum InstType { 643e8d8bef9SDimitry Andric rr2ri_rm, // rr -> ri or rm, commutable 644e8d8bef9SDimitry Andric rr2ir_rm, // rr -> ir or rm 645e8d8bef9SDimitry Andric } InstType; 646e8d8bef9SDimitry Andric 647e8d8bef9SDimitry Andric using namespace llvm::VE; 648e8d8bef9SDimitry Andric #define INSTRKIND(NAME) \ 649e8d8bef9SDimitry Andric case NAME##rr: \ 650e8d8bef9SDimitry Andric NewUseOpcSImm7 = NAME##ri; \ 651e8d8bef9SDimitry Andric NewUseOpcMImm = NAME##rm; \ 652e8d8bef9SDimitry Andric InstType = rr2ri_rm; \ 653e8d8bef9SDimitry Andric break 654e8d8bef9SDimitry Andric #define NCINSTRKIND(NAME) \ 655e8d8bef9SDimitry Andric case NAME##rr: \ 656e8d8bef9SDimitry Andric NewUseOpcSImm7 = NAME##ir; \ 657e8d8bef9SDimitry Andric NewUseOpcMImm = NAME##rm; \ 658e8d8bef9SDimitry Andric InstType = rr2ir_rm; \ 659e8d8bef9SDimitry Andric break 660e8d8bef9SDimitry Andric 661e8d8bef9SDimitry Andric switch (UseMI.getOpcode()) { 662e8d8bef9SDimitry Andric default: 663e8d8bef9SDimitry Andric return false; 664e8d8bef9SDimitry Andric 665e8d8bef9SDimitry Andric INSTRKIND(ADDUL); 666e8d8bef9SDimitry Andric INSTRKIND(ADDSWSX); 667e8d8bef9SDimitry Andric INSTRKIND(ADDSWZX); 668e8d8bef9SDimitry Andric INSTRKIND(ADDSL); 669e8d8bef9SDimitry Andric NCINSTRKIND(SUBUL); 670e8d8bef9SDimitry Andric NCINSTRKIND(SUBSWSX); 671e8d8bef9SDimitry Andric NCINSTRKIND(SUBSWZX); 672e8d8bef9SDimitry Andric NCINSTRKIND(SUBSL); 673e8d8bef9SDimitry Andric INSTRKIND(MULUL); 674e8d8bef9SDimitry Andric INSTRKIND(MULSWSX); 675e8d8bef9SDimitry Andric INSTRKIND(MULSWZX); 676e8d8bef9SDimitry Andric INSTRKIND(MULSL); 677e8d8bef9SDimitry Andric NCINSTRKIND(DIVUL); 678e8d8bef9SDimitry Andric NCINSTRKIND(DIVSWSX); 679e8d8bef9SDimitry Andric NCINSTRKIND(DIVSWZX); 680e8d8bef9SDimitry Andric NCINSTRKIND(DIVSL); 681e8d8bef9SDimitry Andric NCINSTRKIND(CMPUL); 682e8d8bef9SDimitry Andric NCINSTRKIND(CMPSWSX); 683e8d8bef9SDimitry Andric NCINSTRKIND(CMPSWZX); 684e8d8bef9SDimitry Andric NCINSTRKIND(CMPSL); 685e8d8bef9SDimitry Andric INSTRKIND(MAXSWSX); 686e8d8bef9SDimitry Andric INSTRKIND(MAXSWZX); 687e8d8bef9SDimitry Andric INSTRKIND(MAXSL); 688e8d8bef9SDimitry Andric INSTRKIND(MINSWSX); 689e8d8bef9SDimitry Andric INSTRKIND(MINSWZX); 690e8d8bef9SDimitry Andric INSTRKIND(MINSL); 691e8d8bef9SDimitry Andric INSTRKIND(AND); 692e8d8bef9SDimitry Andric INSTRKIND(OR); 693e8d8bef9SDimitry Andric INSTRKIND(XOR); 694e8d8bef9SDimitry Andric INSTRKIND(EQV); 695e8d8bef9SDimitry Andric NCINSTRKIND(NND); 696e8d8bef9SDimitry Andric NCINSTRKIND(MRG); 697e8d8bef9SDimitry Andric } 698e8d8bef9SDimitry Andric 699e8d8bef9SDimitry Andric #undef INSTRKIND 700e8d8bef9SDimitry Andric 701e8d8bef9SDimitry Andric unsigned NewUseOpc; 702e8d8bef9SDimitry Andric unsigned UseIdx; 703e8d8bef9SDimitry Andric bool Commute = false; 704e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "checking UseMI operands\n"); 705e8d8bef9SDimitry Andric switch (InstType) { 706e8d8bef9SDimitry Andric case rr2ri_rm: 707e8d8bef9SDimitry Andric UseIdx = 2; 708e8d8bef9SDimitry Andric if (UseMI.getOperand(1).getReg() == Reg) { 709e8d8bef9SDimitry Andric Commute = true; 710e8d8bef9SDimitry Andric } else { 711e8d8bef9SDimitry Andric assert(UseMI.getOperand(2).getReg() == Reg); 712e8d8bef9SDimitry Andric } 713e8d8bef9SDimitry Andric if (isInt<7>(ImmVal)) { 714e8d8bef9SDimitry Andric // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction 715e8d8bef9SDimitry Andric // holds a simm7 slot. 716e8d8bef9SDimitry Andric NewUseOpc = NewUseOpcSImm7; 717e8d8bef9SDimitry Andric } else if (isMImmVal(ImmVal)) { 718e8d8bef9SDimitry Andric // Similarly, change UseOpc to an instruction holds a mimm slot. 719e8d8bef9SDimitry Andric NewUseOpc = NewUseOpcMImm; 720e8d8bef9SDimitry Andric ImmVal = val2MImm(ImmVal); 721e8d8bef9SDimitry Andric } else 722e8d8bef9SDimitry Andric return false; 723e8d8bef9SDimitry Andric break; 724e8d8bef9SDimitry Andric case rr2ir_rm: 725e8d8bef9SDimitry Andric if (UseMI.getOperand(1).getReg() == Reg) { 726e8d8bef9SDimitry Andric // Check immediate value whether it matchs to the UseMI instruction. 727e8d8bef9SDimitry Andric if (!isInt<7>(ImmVal)) 728e8d8bef9SDimitry Andric return false; 729e8d8bef9SDimitry Andric NewUseOpc = NewUseOpcSImm7; 730e8d8bef9SDimitry Andric UseIdx = 1; 731e8d8bef9SDimitry Andric } else { 732e8d8bef9SDimitry Andric assert(UseMI.getOperand(2).getReg() == Reg); 733e8d8bef9SDimitry Andric // Check immediate value whether it matchs to the UseMI instruction. 734e8d8bef9SDimitry Andric if (!isMImmVal(ImmVal)) 735e8d8bef9SDimitry Andric return false; 736e8d8bef9SDimitry Andric NewUseOpc = NewUseOpcMImm; 737e8d8bef9SDimitry Andric ImmVal = val2MImm(ImmVal); 738e8d8bef9SDimitry Andric UseIdx = 2; 739e8d8bef9SDimitry Andric } 740e8d8bef9SDimitry Andric break; 741e8d8bef9SDimitry Andric } 742e8d8bef9SDimitry Andric 743e8d8bef9SDimitry Andric LLVM_DEBUG(dbgs() << "modifying UseMI\n"); 744e8d8bef9SDimitry Andric bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 745e8d8bef9SDimitry Andric UseMI.setDesc(get(NewUseOpc)); 746e8d8bef9SDimitry Andric if (Commute) { 747e8d8bef9SDimitry Andric UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); 748e8d8bef9SDimitry Andric } 749e8d8bef9SDimitry Andric UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); 750e8d8bef9SDimitry Andric if (DeleteDef) 751e8d8bef9SDimitry Andric DefMI.eraseFromParent(); 752e8d8bef9SDimitry Andric 753e8d8bef9SDimitry Andric return true; 754e8d8bef9SDimitry Andric } 755e8d8bef9SDimitry Andric 7565ffd83dbSDimitry Andric Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 7575ffd83dbSDimitry Andric VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>(); 7585ffd83dbSDimitry Andric Register GlobalBaseReg = VEFI->getGlobalBaseReg(); 7595ffd83dbSDimitry Andric if (GlobalBaseReg != 0) 7605ffd83dbSDimitry Andric return GlobalBaseReg; 7615ffd83dbSDimitry Andric 7625ffd83dbSDimitry Andric // We use %s15 (%got) as a global base register 7635ffd83dbSDimitry Andric GlobalBaseReg = VE::SX15; 7645ffd83dbSDimitry Andric 7655ffd83dbSDimitry Andric // Insert a pseudo instruction to set the GlobalBaseReg into the first 7665ffd83dbSDimitry Andric // MBB of the function 7675ffd83dbSDimitry Andric MachineBasicBlock &FirstMBB = MF->front(); 7685ffd83dbSDimitry Andric MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 7695ffd83dbSDimitry Andric DebugLoc dl; 7705ffd83dbSDimitry Andric BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); 7715ffd83dbSDimitry Andric VEFI->setGlobalBaseReg(GlobalBaseReg); 7725ffd83dbSDimitry Andric return GlobalBaseReg; 7735ffd83dbSDimitry Andric } 774480093f4SDimitry Andric 775e8d8bef9SDimitry Andric static Register getVM512Upper(Register reg) { 776e8d8bef9SDimitry Andric return (reg - VE::VMP0) * 2 + VE::VM0; 777e8d8bef9SDimitry Andric } 778e8d8bef9SDimitry Andric 779e8d8bef9SDimitry Andric static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; } 780e8d8bef9SDimitry Andric 781e8d8bef9SDimitry Andric // Expand pseudo logical vector instructions for VM512 registers. 782e8d8bef9SDimitry Andric static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID) { 783e8d8bef9SDimitry Andric MachineBasicBlock *MBB = MI.getParent(); 784e8d8bef9SDimitry Andric DebugLoc DL = MI.getDebugLoc(); 785e8d8bef9SDimitry Andric 786e8d8bef9SDimitry Andric Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 787e8d8bef9SDimitry Andric Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 788e8d8bef9SDimitry Andric Register VMYu = getVM512Upper(MI.getOperand(1).getReg()); 789e8d8bef9SDimitry Andric Register VMYl = getVM512Lower(MI.getOperand(1).getReg()); 790e8d8bef9SDimitry Andric 791e8d8bef9SDimitry Andric switch (MI.getOpcode()) { 792e8d8bef9SDimitry Andric default: { 793e8d8bef9SDimitry Andric Register VMZu = getVM512Upper(MI.getOperand(2).getReg()); 794e8d8bef9SDimitry Andric Register VMZl = getVM512Lower(MI.getOperand(2).getReg()); 795e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); 796e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); 797e8d8bef9SDimitry Andric break; 798e8d8bef9SDimitry Andric } 799e8d8bef9SDimitry Andric case VE::NEGMy: 800e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); 801e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); 802e8d8bef9SDimitry Andric break; 803e8d8bef9SDimitry Andric } 804e8d8bef9SDimitry Andric MI.eraseFromParent(); 805e8d8bef9SDimitry Andric } 806e8d8bef9SDimitry Andric 807e8d8bef9SDimitry Andric static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, 808e8d8bef9SDimitry Andric bool Upper) { 809e8d8bef9SDimitry Andric // VM512 810e8d8bef9SDimitry Andric MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg()) 811e8d8bef9SDimitry Andric : getVM512Lower(MI.getOperand(0).getReg())); 812e8d8bef9SDimitry Andric 813e8d8bef9SDimitry Andric switch (MI.getNumExplicitOperands()) { 814e8d8bef9SDimitry Andric default: 815e8d8bef9SDimitry Andric report_fatal_error("unexpected number of operands for pvfmk"); 816e8d8bef9SDimitry Andric case 2: // _Ml: VM512, VL 817e8d8bef9SDimitry Andric // VL 818e8d8bef9SDimitry Andric MIB.addReg(MI.getOperand(1).getReg()); 819e8d8bef9SDimitry Andric break; 820e8d8bef9SDimitry Andric case 4: // _Mvl: VM512, CC, VR, VL 821e8d8bef9SDimitry Andric // CC 822e8d8bef9SDimitry Andric MIB.addImm(MI.getOperand(1).getImm()); 823e8d8bef9SDimitry Andric // VR 824e8d8bef9SDimitry Andric MIB.addReg(MI.getOperand(2).getReg()); 825e8d8bef9SDimitry Andric // VL 826e8d8bef9SDimitry Andric MIB.addReg(MI.getOperand(3).getReg()); 827e8d8bef9SDimitry Andric break; 828e8d8bef9SDimitry Andric case 5: // _MvMl: VM512, CC, VR, VM512, VL 829e8d8bef9SDimitry Andric // CC 830e8d8bef9SDimitry Andric MIB.addImm(MI.getOperand(1).getImm()); 831e8d8bef9SDimitry Andric // VR 832e8d8bef9SDimitry Andric MIB.addReg(MI.getOperand(2).getReg()); 833e8d8bef9SDimitry Andric // VM512 834e8d8bef9SDimitry Andric MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg()) 835e8d8bef9SDimitry Andric : getVM512Lower(MI.getOperand(3).getReg())); 836e8d8bef9SDimitry Andric // VL 837e8d8bef9SDimitry Andric MIB.addReg(MI.getOperand(4).getReg()); 838e8d8bef9SDimitry Andric break; 839e8d8bef9SDimitry Andric } 840e8d8bef9SDimitry Andric } 841e8d8bef9SDimitry Andric 842e8d8bef9SDimitry Andric static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI) { 843e8d8bef9SDimitry Andric // replace to pvfmk.w.up and pvfmk.w.lo 844e8d8bef9SDimitry Andric // replace to pvfmk.s.up and pvfmk.s.lo 845e8d8bef9SDimitry Andric 84681ad6265SDimitry Andric static const std::pair<unsigned, std::pair<unsigned, unsigned>> VFMKMap[] = { 847e8d8bef9SDimitry Andric {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}}, 848e8d8bef9SDimitry Andric {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}}, 849e8d8bef9SDimitry Andric {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}}, 850e8d8bef9SDimitry Andric {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}}, 851e8d8bef9SDimitry Andric {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}}, 852e8d8bef9SDimitry Andric {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}}, 853e8d8bef9SDimitry Andric }; 854e8d8bef9SDimitry Andric 855e8d8bef9SDimitry Andric unsigned Opcode = MI.getOpcode(); 856e8d8bef9SDimitry Andric 85781ad6265SDimitry Andric const auto *Found = 85881ad6265SDimitry Andric llvm::find_if(VFMKMap, [&](auto P) { return P.first == Opcode; }); 85981ad6265SDimitry Andric if (Found == std::end(VFMKMap)) 860e8d8bef9SDimitry Andric report_fatal_error("unexpected opcode for pseudo vfmk"); 861e8d8bef9SDimitry Andric 862e8d8bef9SDimitry Andric unsigned OpcodeUpper = (*Found).second.first; 863e8d8bef9SDimitry Andric unsigned OpcodeLower = (*Found).second.second; 864e8d8bef9SDimitry Andric 865e8d8bef9SDimitry Andric MachineBasicBlock *MBB = MI.getParent(); 866e8d8bef9SDimitry Andric DebugLoc DL = MI.getDebugLoc(); 867e8d8bef9SDimitry Andric 868e8d8bef9SDimitry Andric MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper)); 869e8d8bef9SDimitry Andric addOperandsForVFMK(Bu, MI, /* Upper */ true); 870e8d8bef9SDimitry Andric MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower)); 871e8d8bef9SDimitry Andric addOperandsForVFMK(Bl, MI, /* Upper */ false); 872e8d8bef9SDimitry Andric 873e8d8bef9SDimitry Andric MI.eraseFromParent(); 874e8d8bef9SDimitry Andric } 875e8d8bef9SDimitry Andric 876480093f4SDimitry Andric bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 877480093f4SDimitry Andric switch (MI.getOpcode()) { 878480093f4SDimitry Andric case VE::EXTEND_STACK: { 879480093f4SDimitry Andric return expandExtendStackPseudo(MI); 880480093f4SDimitry Andric } 881480093f4SDimitry Andric case VE::EXTEND_STACK_GUARD: { 882480093f4SDimitry Andric MI.eraseFromParent(); // The pseudo instruction is gone now. 883480093f4SDimitry Andric return true; 884480093f4SDimitry Andric } 8855ffd83dbSDimitry Andric case VE::GETSTACKTOP: { 8865ffd83dbSDimitry Andric return expandGetStackTopPseudo(MI); 8875ffd83dbSDimitry Andric } 888e8d8bef9SDimitry Andric 889e8d8bef9SDimitry Andric case VE::ANDMyy: 890e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::ANDMmm)); 891e8d8bef9SDimitry Andric return true; 892e8d8bef9SDimitry Andric case VE::ORMyy: 893e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::ORMmm)); 894e8d8bef9SDimitry Andric return true; 895e8d8bef9SDimitry Andric case VE::XORMyy: 896e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::XORMmm)); 897e8d8bef9SDimitry Andric return true; 898e8d8bef9SDimitry Andric case VE::EQVMyy: 899e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::EQVMmm)); 900e8d8bef9SDimitry Andric return true; 901e8d8bef9SDimitry Andric case VE::NNDMyy: 902e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::NNDMmm)); 903e8d8bef9SDimitry Andric return true; 904e8d8bef9SDimitry Andric case VE::NEGMy: 905e8d8bef9SDimitry Andric expandPseudoLogM(MI, get(VE::NEGMm)); 906e8d8bef9SDimitry Andric return true; 907e8d8bef9SDimitry Andric 908e8d8bef9SDimitry Andric case VE::LVMyir: 909e8d8bef9SDimitry Andric case VE::LVMyim: 910e8d8bef9SDimitry Andric case VE::LVMyir_y: 911e8d8bef9SDimitry Andric case VE::LVMyim_y: { 912e8d8bef9SDimitry Andric Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 913e8d8bef9SDimitry Andric Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 914e8d8bef9SDimitry Andric int64_t Imm = MI.getOperand(1).getImm(); 915e8d8bef9SDimitry Andric bool IsSrcReg = 916e8d8bef9SDimitry Andric MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y; 917e8d8bef9SDimitry Andric Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister; 918e8d8bef9SDimitry Andric int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm(); 919e8d8bef9SDimitry Andric bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; 920e8d8bef9SDimitry Andric Register VMX = VMXl; 921e8d8bef9SDimitry Andric if (Imm >= 4) { 922e8d8bef9SDimitry Andric VMX = VMXu; 923e8d8bef9SDimitry Andric Imm -= 4; 924e8d8bef9SDimitry Andric } 925e8d8bef9SDimitry Andric MachineBasicBlock *MBB = MI.getParent(); 926e8d8bef9SDimitry Andric DebugLoc DL = MI.getDebugLoc(); 927e8d8bef9SDimitry Andric switch (MI.getOpcode()) { 928e8d8bef9SDimitry Andric case VE::LVMyir: 929e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, get(VE::LVMir)) 930e8d8bef9SDimitry Andric .addDef(VMX) 931e8d8bef9SDimitry Andric .addImm(Imm) 932e8d8bef9SDimitry Andric .addReg(Src, getKillRegState(KillSrc)); 933e8d8bef9SDimitry Andric break; 934e8d8bef9SDimitry Andric case VE::LVMyim: 935e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, get(VE::LVMim)) 936e8d8bef9SDimitry Andric .addDef(VMX) 937e8d8bef9SDimitry Andric .addImm(Imm) 938e8d8bef9SDimitry Andric .addImm(MImm); 939e8d8bef9SDimitry Andric break; 940e8d8bef9SDimitry Andric case VE::LVMyir_y: 941e8d8bef9SDimitry Andric assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 942e8d8bef9SDimitry Andric "LVMyir_y has different register in 3rd operand"); 943e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, get(VE::LVMir_m)) 944e8d8bef9SDimitry Andric .addDef(VMX) 945e8d8bef9SDimitry Andric .addImm(Imm) 946e8d8bef9SDimitry Andric .addReg(Src, getKillRegState(KillSrc)) 947e8d8bef9SDimitry Andric .addReg(VMX); 948e8d8bef9SDimitry Andric break; 949e8d8bef9SDimitry Andric case VE::LVMyim_y: 950e8d8bef9SDimitry Andric assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 951e8d8bef9SDimitry Andric "LVMyim_y has different register in 3rd operand"); 952e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, get(VE::LVMim_m)) 953e8d8bef9SDimitry Andric .addDef(VMX) 954e8d8bef9SDimitry Andric .addImm(Imm) 955e8d8bef9SDimitry Andric .addImm(MImm) 956e8d8bef9SDimitry Andric .addReg(VMX); 957e8d8bef9SDimitry Andric break; 958e8d8bef9SDimitry Andric } 959e8d8bef9SDimitry Andric MI.eraseFromParent(); 960e8d8bef9SDimitry Andric return true; 961e8d8bef9SDimitry Andric } 962e8d8bef9SDimitry Andric case VE::SVMyi: { 963e8d8bef9SDimitry Andric Register Dest = MI.getOperand(0).getReg(); 964e8d8bef9SDimitry Andric Register VMZu = getVM512Upper(MI.getOperand(1).getReg()); 965e8d8bef9SDimitry Andric Register VMZl = getVM512Lower(MI.getOperand(1).getReg()); 966e8d8bef9SDimitry Andric bool KillSrc = MI.getOperand(1).isKill(); 967e8d8bef9SDimitry Andric int64_t Imm = MI.getOperand(2).getImm(); 968e8d8bef9SDimitry Andric Register VMZ = VMZl; 969e8d8bef9SDimitry Andric if (Imm >= 4) { 970e8d8bef9SDimitry Andric VMZ = VMZu; 971e8d8bef9SDimitry Andric Imm -= 4; 972e8d8bef9SDimitry Andric } 973e8d8bef9SDimitry Andric MachineBasicBlock *MBB = MI.getParent(); 974e8d8bef9SDimitry Andric DebugLoc DL = MI.getDebugLoc(); 975e8d8bef9SDimitry Andric MachineInstrBuilder MIB = 976e8d8bef9SDimitry Andric BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm); 977e8d8bef9SDimitry Andric MachineInstr *Inst = MIB.getInstr(); 978e8d8bef9SDimitry Andric if (KillSrc) { 979e8d8bef9SDimitry Andric const TargetRegisterInfo *TRI = &getRegisterInfo(); 980e8d8bef9SDimitry Andric Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true); 981e8d8bef9SDimitry Andric } 9824824e7fdSDimitry Andric MI.eraseFromParent(); 983e8d8bef9SDimitry Andric return true; 984e8d8bef9SDimitry Andric } 985e8d8bef9SDimitry Andric case VE::VFMKyal: 986e8d8bef9SDimitry Andric case VE::VFMKynal: 987e8d8bef9SDimitry Andric case VE::VFMKWyvl: 988e8d8bef9SDimitry Andric case VE::VFMKWyvyl: 989e8d8bef9SDimitry Andric case VE::VFMKSyvl: 990e8d8bef9SDimitry Andric case VE::VFMKSyvyl: 991e8d8bef9SDimitry Andric expandPseudoVFMK(*this, MI); 9924824e7fdSDimitry Andric return true; 993480093f4SDimitry Andric } 994480093f4SDimitry Andric return false; 995480093f4SDimitry Andric } 996480093f4SDimitry Andric 997480093f4SDimitry Andric bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const { 998480093f4SDimitry Andric MachineBasicBlock &MBB = *MI.getParent(); 999480093f4SDimitry Andric MachineFunction &MF = *MBB.getParent(); 10005ffd83dbSDimitry Andric const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 10015ffd83dbSDimitry Andric const VEInstrInfo &TII = *STI.getInstrInfo(); 1002480093f4SDimitry Andric DebugLoc dl = MBB.findDebugLoc(MI); 1003480093f4SDimitry Andric 1004480093f4SDimitry Andric // Create following instructions and multiple basic blocks. 1005480093f4SDimitry Andric // 1006480093f4SDimitry Andric // thisBB: 1007480093f4SDimitry Andric // brge.l.t %sp, %sl, sinkBB 1008480093f4SDimitry Andric // syscallBB: 1009480093f4SDimitry Andric // ld %s61, 0x18(, %tp) // load param area 1010480093f4SDimitry Andric // or %s62, 0, %s0 // spill the value of %s0 1011480093f4SDimitry Andric // lea %s63, 0x13b // syscall # of grow 1012480093f4SDimitry Andric // shm.l %s63, 0x0(%s61) // store syscall # at addr:0 1013480093f4SDimitry Andric // shm.l %sl, 0x8(%s61) // store old limit at addr:8 1014480093f4SDimitry Andric // shm.l %sp, 0x10(%s61) // store new limit at addr:16 1015480093f4SDimitry Andric // monc // call monitor 1016480093f4SDimitry Andric // or %s0, 0, %s62 // restore the value of %s0 1017480093f4SDimitry Andric // sinkBB: 1018480093f4SDimitry Andric 1019480093f4SDimitry Andric // Create new MBB 1020480093f4SDimitry Andric MachineBasicBlock *BB = &MBB; 1021480093f4SDimitry Andric const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1022480093f4SDimitry Andric MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB); 1023480093f4SDimitry Andric MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB); 1024480093f4SDimitry Andric MachineFunction::iterator It = ++(BB->getIterator()); 1025480093f4SDimitry Andric MF.insert(It, syscallMBB); 1026480093f4SDimitry Andric MF.insert(It, sinkMBB); 1027480093f4SDimitry Andric 1028480093f4SDimitry Andric // Transfer the remainder of BB and its successor edges to sinkMBB. 1029480093f4SDimitry Andric sinkMBB->splice(sinkMBB->begin(), BB, 1030480093f4SDimitry Andric std::next(std::next(MachineBasicBlock::iterator(MI))), 1031480093f4SDimitry Andric BB->end()); 1032480093f4SDimitry Andric sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1033480093f4SDimitry Andric 1034480093f4SDimitry Andric // Next, add the true and fallthrough blocks as its successors. 1035480093f4SDimitry Andric BB->addSuccessor(syscallMBB); 1036480093f4SDimitry Andric BB->addSuccessor(sinkMBB); 10375ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) 1038480093f4SDimitry Andric .addImm(VECC::CC_IGE) 1039480093f4SDimitry Andric .addReg(VE::SX11) // %sp 1040480093f4SDimitry Andric .addReg(VE::SX8) // %sl 1041480093f4SDimitry Andric .addMBB(sinkMBB); 1042480093f4SDimitry Andric 1043480093f4SDimitry Andric BB = syscallMBB; 1044480093f4SDimitry Andric 1045480093f4SDimitry Andric // Update machine-CFG edges 1046480093f4SDimitry Andric BB->addSuccessor(sinkMBB); 1047480093f4SDimitry Andric 10485ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) 1049480093f4SDimitry Andric .addReg(VE::SX14) 10505ffd83dbSDimitry Andric .addImm(0) 1051480093f4SDimitry Andric .addImm(0x18); 1052480093f4SDimitry Andric BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 1053480093f4SDimitry Andric .addReg(VE::SX0) 1054480093f4SDimitry Andric .addImm(0); 10555ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) 10565ffd83dbSDimitry Andric .addImm(0) 10575ffd83dbSDimitry Andric .addImm(0) 1058480093f4SDimitry Andric .addImm(0x13b); 10595ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::SHMLri)) 1060480093f4SDimitry Andric .addReg(VE::SX61) 1061480093f4SDimitry Andric .addImm(0) 1062480093f4SDimitry Andric .addReg(VE::SX63); 10635ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::SHMLri)) 1064480093f4SDimitry Andric .addReg(VE::SX61) 1065480093f4SDimitry Andric .addImm(8) 1066480093f4SDimitry Andric .addReg(VE::SX8); 10675ffd83dbSDimitry Andric BuildMI(BB, dl, TII.get(VE::SHMLri)) 1068480093f4SDimitry Andric .addReg(VE::SX61) 1069480093f4SDimitry Andric .addImm(16) 1070480093f4SDimitry Andric .addReg(VE::SX11); 1071480093f4SDimitry Andric BuildMI(BB, dl, TII.get(VE::MONC)); 1072480093f4SDimitry Andric 1073480093f4SDimitry Andric BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0) 1074480093f4SDimitry Andric .addReg(VE::SX62) 1075480093f4SDimitry Andric .addImm(0); 1076480093f4SDimitry Andric 1077480093f4SDimitry Andric MI.eraseFromParent(); // The pseudo instruction is gone now. 1078480093f4SDimitry Andric return true; 1079480093f4SDimitry Andric } 10805ffd83dbSDimitry Andric 10815ffd83dbSDimitry Andric bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const { 10825ffd83dbSDimitry Andric MachineBasicBlock *MBB = MI.getParent(); 10835ffd83dbSDimitry Andric MachineFunction &MF = *MBB->getParent(); 10845ffd83dbSDimitry Andric const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 10855ffd83dbSDimitry Andric const VEInstrInfo &TII = *STI.getInstrInfo(); 10865ffd83dbSDimitry Andric DebugLoc DL = MBB->findDebugLoc(MI); 10875ffd83dbSDimitry Andric 10885ffd83dbSDimitry Andric // Create following instruction 10895ffd83dbSDimitry Andric // 10905ffd83dbSDimitry Andric // dst = %sp + target specific frame + the size of parameter area 10915ffd83dbSDimitry Andric 10925ffd83dbSDimitry Andric const MachineFrameInfo &MFI = MF.getFrameInfo(); 10935ffd83dbSDimitry Andric const VEFrameLowering &TFL = *STI.getFrameLowering(); 10945ffd83dbSDimitry Andric 1095e8d8bef9SDimitry Andric // The VE ABI requires a reserved area at the top of stack as described 1096e8d8bef9SDimitry Andric // in VEFrameLowering.cpp. So, we adjust it here. 10975ffd83dbSDimitry Andric unsigned NumBytes = STI.getAdjustedFrameSize(0); 10985ffd83dbSDimitry Andric 10995ffd83dbSDimitry Andric // Also adds the size of parameter area. 11005ffd83dbSDimitry Andric if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF)) 11015ffd83dbSDimitry Andric NumBytes += MFI.getMaxCallFrameSize(); 11025ffd83dbSDimitry Andric 11035ffd83dbSDimitry Andric BuildMI(*MBB, MI, DL, TII.get(VE::LEArii)) 11045ffd83dbSDimitry Andric .addDef(MI.getOperand(0).getReg()) 11055ffd83dbSDimitry Andric .addReg(VE::SX11) 11065ffd83dbSDimitry Andric .addImm(0) 11075ffd83dbSDimitry Andric .addImm(NumBytes); 11085ffd83dbSDimitry Andric 11095ffd83dbSDimitry Andric MI.eraseFromParent(); // The pseudo instruction is gone now. 11105ffd83dbSDimitry Andric return true; 11115ffd83dbSDimitry Andric } 1112