1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass makes sure that all branches are in range. There are several ways 10 // in which this could be done. One aggressive approach is to assume that all 11 // branches are in range and successively replace those that turn out not 12 // to be in range with a longer form (branch relaxation). A simple 13 // implementation is to continually walk through the function relaxing 14 // branches until no more changes are needed and a fixed point is reached. 15 // However, in the pathological worst case, this implementation is 16 // quadratic in the number of blocks; relaxing branch N can make branch N-1 17 // go out of range, which in turn can make branch N-2 go out of range, 18 // and so on. 19 // 20 // An alternative approach is to assume that all branches must be 21 // converted to their long forms, then reinstate the short forms of 22 // branches that, even under this pessimistic assumption, turn out to be 23 // in range (branch shortening). This too can be implemented as a function 24 // walk that is repeated until a fixed point is reached. In general, 25 // the result of shortening is not as good as that of relaxation, and 26 // shortening is also quadratic in the worst case; shortening branch N 27 // can bring branch N-1 in range of the short form, which in turn can do 28 // the same for branch N-2, and so on. The main advantage of shortening 29 // is that each walk through the function produces valid code, so it is 30 // possible to stop at any point after the first walk. The quadraticness 31 // could therefore be handled with a maximum pass count, although the 32 // question then becomes: what maximum count should be used? 33 // 34 // On SystemZ, long branches are only needed for functions bigger than 64k, 35 // which are relatively rare to begin with, and the long branch sequences 36 // are actually relatively cheap. It therefore doesn't seem worth spending 37 // much compilation time on the problem. Instead, the approach we take is: 38 // 39 // (1) Work out the address that each block would have if no branches 40 // need relaxing. Exit the pass early if all branches are in range 41 // according to this assumption. 42 // 43 // (2) Work out the address that each block would have if all branches 44 // need relaxing. 45 // 46 // (3) Walk through the block calculating the final address of each instruction 47 // and relaxing those that need to be relaxed. For backward branches, 48 // this check uses the final address of the target block, as calculated 49 // earlier in the walk. For forward branches, this check uses the 50 // address of the target block that was calculated in (2). Both checks 51 // give a conservatively-correct range. 52 // 53 //===----------------------------------------------------------------------===// 54 55 #include "SystemZ.h" 56 #include "SystemZInstrInfo.h" 57 #include "SystemZTargetMachine.h" 58 #include "llvm/ADT/SmallVector.h" 59 #include "llvm/ADT/Statistic.h" 60 #include "llvm/ADT/StringRef.h" 61 #include "llvm/CodeGen/MachineBasicBlock.h" 62 #include "llvm/CodeGen/MachineFunction.h" 63 #include "llvm/CodeGen/MachineFunctionPass.h" 64 #include "llvm/CodeGen/MachineInstr.h" 65 #include "llvm/CodeGen/MachineInstrBuilder.h" 66 #include "llvm/IR/DebugLoc.h" 67 #include "llvm/Support/ErrorHandling.h" 68 #include <cassert> 69 #include <cstdint> 70 71 using namespace llvm; 72 73 #define DEBUG_TYPE "systemz-long-branch" 74 75 STATISTIC(LongBranches, "Number of long branches."); 76 77 namespace { 78 79 // Represents positional information about a basic block. 80 struct MBBInfo { 81 // The address that we currently assume the block has. 82 uint64_t Address = 0; 83 84 // The size of the block in bytes, excluding terminators. 85 // This value never changes. 86 uint64_t Size = 0; 87 88 // The minimum alignment of the block. 89 // This value never changes. 90 Align Alignment; 91 92 // The number of terminators in this block. This value never changes. 93 unsigned NumTerminators = 0; 94 95 MBBInfo() = default; 96 }; 97 98 // Represents the state of a block terminator. 99 struct TerminatorInfo { 100 // If this terminator is a relaxable branch, this points to the branch 101 // instruction, otherwise it is null. 102 MachineInstr *Branch = nullptr; 103 104 // The address that we currently assume the terminator has. 105 uint64_t Address = 0; 106 107 // The current size of the terminator in bytes. 108 uint64_t Size = 0; 109 110 // If Branch is nonnull, this is the number of the target block, 111 // otherwise it is unused. 112 unsigned TargetBlock = 0; 113 114 // If Branch is nonnull, this is the length of the longest relaxed form, 115 // otherwise it is zero. 116 unsigned ExtraRelaxSize = 0; 117 118 TerminatorInfo() = default; 119 }; 120 121 // Used to keep track of the current position while iterating over the blocks. 122 struct BlockPosition { 123 // The address that we assume this position has. 124 uint64_t Address = 0; 125 126 // The number of low bits in Address that are known to be the same 127 // as the runtime address. 128 unsigned KnownBits; 129 130 BlockPosition(unsigned InitialLogAlignment) 131 : KnownBits(InitialLogAlignment) {} 132 }; 133 134 class SystemZLongBranch : public MachineFunctionPass { 135 public: 136 static char ID; 137 138 SystemZLongBranch(const SystemZTargetMachine &tm) 139 : MachineFunctionPass(ID) {} 140 141 StringRef getPassName() const override { return "SystemZ Long Branch"; } 142 143 bool runOnMachineFunction(MachineFunction &F) override; 144 145 MachineFunctionProperties getRequiredProperties() const override { 146 return MachineFunctionProperties().set( 147 MachineFunctionProperties::Property::NoVRegs); 148 } 149 150 private: 151 void skipNonTerminators(BlockPosition &Position, MBBInfo &Block); 152 void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator, 153 bool AssumeRelaxed); 154 TerminatorInfo describeTerminator(MachineInstr &MI); 155 uint64_t initMBBInfo(); 156 bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address); 157 bool mustRelaxABranch(); 158 void setWorstCaseAddresses(); 159 void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode); 160 void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode); 161 void relaxBranch(TerminatorInfo &Terminator); 162 void relaxBranches(); 163 164 const SystemZInstrInfo *TII = nullptr; 165 MachineFunction *MF = nullptr; 166 SmallVector<MBBInfo, 16> MBBs; 167 SmallVector<TerminatorInfo, 16> Terminators; 168 }; 169 170 char SystemZLongBranch::ID = 0; 171 172 const uint64_t MaxBackwardRange = 0x10000; 173 const uint64_t MaxForwardRange = 0xfffe; 174 175 } // end anonymous namespace 176 177 // Position describes the state immediately before Block. Update Block 178 // accordingly and move Position to the end of the block's non-terminator 179 // instructions. 180 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position, 181 MBBInfo &Block) { 182 if (Log2(Block.Alignment) > Position.KnownBits) { 183 // When calculating the address of Block, we need to conservatively 184 // assume that Block had the worst possible misalignment. 185 Position.Address += 186 (Block.Alignment.value() - (uint64_t(1) << Position.KnownBits)); 187 Position.KnownBits = Log2(Block.Alignment); 188 } 189 190 // Align the addresses. 191 Position.Address = alignTo(Position.Address, Block.Alignment); 192 193 // Record the block's position. 194 Block.Address = Position.Address; 195 196 // Move past the non-terminators in the block. 197 Position.Address += Block.Size; 198 } 199 200 // Position describes the state immediately before Terminator. 201 // Update Terminator accordingly and move Position past it. 202 // Assume that Terminator will be relaxed if AssumeRelaxed. 203 void SystemZLongBranch::skipTerminator(BlockPosition &Position, 204 TerminatorInfo &Terminator, 205 bool AssumeRelaxed) { 206 Terminator.Address = Position.Address; 207 Position.Address += Terminator.Size; 208 if (AssumeRelaxed) 209 Position.Address += Terminator.ExtraRelaxSize; 210 } 211 212 static unsigned getInstSizeInBytes(const MachineInstr &MI, 213 const SystemZInstrInfo *TII) { 214 unsigned Size = TII->getInstSizeInBytes(MI); 215 assert((Size || 216 // These do not have a size: 217 MI.isDebugOrPseudoInstr() || MI.isPosition() || MI.isKill() || 218 MI.isImplicitDef() || MI.getOpcode() == SystemZ::MemBarrier || 219 // These have a size that may be zero: 220 MI.isInlineAsm() || MI.getOpcode() == SystemZ::STACKMAP || 221 MI.getOpcode() == SystemZ::PATCHPOINT) && 222 "Missing size value for instruction."); 223 return Size; 224 } 225 226 // Return a description of terminator instruction MI. 227 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) { 228 TerminatorInfo Terminator; 229 Terminator.Size = getInstSizeInBytes(MI, TII); 230 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) { 231 switch (MI.getOpcode()) { 232 case SystemZ::J: 233 // Relaxes to JG, which is 2 bytes longer. 234 Terminator.ExtraRelaxSize = 2; 235 break; 236 case SystemZ::BRC: 237 // Relaxes to BRCL, which is 2 bytes longer. 238 Terminator.ExtraRelaxSize = 2; 239 break; 240 case SystemZ::BRCT: 241 case SystemZ::BRCTG: 242 // Relaxes to A(G)HI and BRCL, which is 6 bytes longer. 243 Terminator.ExtraRelaxSize = 6; 244 break; 245 case SystemZ::BRCTH: 246 // Never needs to be relaxed. 247 Terminator.ExtraRelaxSize = 0; 248 break; 249 case SystemZ::CRJ: 250 case SystemZ::CLRJ: 251 // Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer. 252 Terminator.ExtraRelaxSize = 2; 253 break; 254 case SystemZ::CGRJ: 255 case SystemZ::CLGRJ: 256 // Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer. 257 Terminator.ExtraRelaxSize = 4; 258 break; 259 case SystemZ::CIJ: 260 case SystemZ::CGIJ: 261 // Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer. 262 Terminator.ExtraRelaxSize = 4; 263 break; 264 case SystemZ::CLIJ: 265 case SystemZ::CLGIJ: 266 // Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer. 267 Terminator.ExtraRelaxSize = 6; 268 break; 269 default: 270 llvm_unreachable("Unrecognized branch instruction"); 271 } 272 Terminator.Branch = &MI; 273 Terminator.TargetBlock = 274 TII->getBranchInfo(MI).getMBBTarget()->getNumber(); 275 } 276 return Terminator; 277 } 278 279 // Fill MBBs and Terminators, setting the addresses on the assumption 280 // that no branches need relaxation. Return the size of the function under 281 // this assumption. 282 uint64_t SystemZLongBranch::initMBBInfo() { 283 MF->RenumberBlocks(); 284 unsigned NumBlocks = MF->size(); 285 286 MBBs.clear(); 287 MBBs.resize(NumBlocks); 288 289 Terminators.clear(); 290 Terminators.reserve(NumBlocks); 291 292 BlockPosition Position(Log2(MF->getAlignment())); 293 for (unsigned I = 0; I < NumBlocks; ++I) { 294 MachineBasicBlock *MBB = MF->getBlockNumbered(I); 295 MBBInfo &Block = MBBs[I]; 296 297 // Record the alignment, for quick access. 298 Block.Alignment = MBB->getAlignment(); 299 300 // Calculate the size of the fixed part of the block. 301 MachineBasicBlock::iterator MI = MBB->begin(); 302 MachineBasicBlock::iterator End = MBB->end(); 303 while (MI != End && !MI->isTerminator()) { 304 Block.Size += getInstSizeInBytes(*MI, TII); 305 ++MI; 306 } 307 skipNonTerminators(Position, Block); 308 309 // Add the terminators. 310 while (MI != End) { 311 if (!MI->isDebugInstr()) { 312 assert(MI->isTerminator() && "Terminator followed by non-terminator"); 313 Terminators.push_back(describeTerminator(*MI)); 314 skipTerminator(Position, Terminators.back(), false); 315 ++Block.NumTerminators; 316 } 317 ++MI; 318 } 319 } 320 321 return Position.Address; 322 } 323 324 // Return true if, under current assumptions, Terminator would need to be 325 // relaxed if it were placed at address Address. 326 bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator, 327 uint64_t Address) { 328 if (!Terminator.Branch || Terminator.ExtraRelaxSize == 0) 329 return false; 330 331 const MBBInfo &Target = MBBs[Terminator.TargetBlock]; 332 if (Address >= Target.Address) { 333 if (Address - Target.Address <= MaxBackwardRange) 334 return false; 335 } else { 336 if (Target.Address - Address <= MaxForwardRange) 337 return false; 338 } 339 340 return true; 341 } 342 343 // Return true if, under current assumptions, any terminator needs 344 // to be relaxed. 345 bool SystemZLongBranch::mustRelaxABranch() { 346 for (auto &Terminator : Terminators) 347 if (mustRelaxBranch(Terminator, Terminator.Address)) 348 return true; 349 return false; 350 } 351 352 // Set the address of each block on the assumption that all branches 353 // must be long. 354 void SystemZLongBranch::setWorstCaseAddresses() { 355 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); 356 BlockPosition Position(Log2(MF->getAlignment())); 357 for (auto &Block : MBBs) { 358 skipNonTerminators(Position, Block); 359 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { 360 skipTerminator(Position, *TI, true); 361 ++TI; 362 } 363 } 364 } 365 366 // Split BRANCH ON COUNT MI into the addition given by AddOpcode followed 367 // by a BRCL on the result. 368 void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI, 369 unsigned AddOpcode) { 370 MachineBasicBlock *MBB = MI->getParent(); 371 DebugLoc DL = MI->getDebugLoc(); 372 BuildMI(*MBB, MI, DL, TII->get(AddOpcode)) 373 .add(MI->getOperand(0)) 374 .add(MI->getOperand(1)) 375 .addImm(-1); 376 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 377 .addImm(SystemZ::CCMASK_ICMP) 378 .addImm(SystemZ::CCMASK_CMP_NE) 379 .add(MI->getOperand(2)); 380 // The implicit use of CC is a killing use. 381 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 382 MI->eraseFromParent(); 383 } 384 385 // Split MI into the comparison given by CompareOpcode followed 386 // a BRCL on the result. 387 void SystemZLongBranch::splitCompareBranch(MachineInstr *MI, 388 unsigned CompareOpcode) { 389 MachineBasicBlock *MBB = MI->getParent(); 390 DebugLoc DL = MI->getDebugLoc(); 391 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode)) 392 .add(MI->getOperand(0)) 393 .add(MI->getOperand(1)); 394 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 395 .addImm(SystemZ::CCMASK_ICMP) 396 .add(MI->getOperand(2)) 397 .add(MI->getOperand(3)); 398 // The implicit use of CC is a killing use. 399 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 400 MI->eraseFromParent(); 401 } 402 403 // Relax the branch described by Terminator. 404 void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) { 405 MachineInstr *Branch = Terminator.Branch; 406 switch (Branch->getOpcode()) { 407 case SystemZ::J: 408 Branch->setDesc(TII->get(SystemZ::JG)); 409 break; 410 case SystemZ::BRC: 411 Branch->setDesc(TII->get(SystemZ::BRCL)); 412 break; 413 case SystemZ::BRCT: 414 splitBranchOnCount(Branch, SystemZ::AHI); 415 break; 416 case SystemZ::BRCTG: 417 splitBranchOnCount(Branch, SystemZ::AGHI); 418 break; 419 case SystemZ::CRJ: 420 splitCompareBranch(Branch, SystemZ::CR); 421 break; 422 case SystemZ::CGRJ: 423 splitCompareBranch(Branch, SystemZ::CGR); 424 break; 425 case SystemZ::CIJ: 426 splitCompareBranch(Branch, SystemZ::CHI); 427 break; 428 case SystemZ::CGIJ: 429 splitCompareBranch(Branch, SystemZ::CGHI); 430 break; 431 case SystemZ::CLRJ: 432 splitCompareBranch(Branch, SystemZ::CLR); 433 break; 434 case SystemZ::CLGRJ: 435 splitCompareBranch(Branch, SystemZ::CLGR); 436 break; 437 case SystemZ::CLIJ: 438 splitCompareBranch(Branch, SystemZ::CLFI); 439 break; 440 case SystemZ::CLGIJ: 441 splitCompareBranch(Branch, SystemZ::CLGFI); 442 break; 443 default: 444 llvm_unreachable("Unrecognized branch"); 445 } 446 447 Terminator.Size += Terminator.ExtraRelaxSize; 448 Terminator.ExtraRelaxSize = 0; 449 Terminator.Branch = nullptr; 450 451 ++LongBranches; 452 } 453 454 // Run a shortening pass and relax any branches that need to be relaxed. 455 void SystemZLongBranch::relaxBranches() { 456 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); 457 BlockPosition Position(Log2(MF->getAlignment())); 458 for (auto &Block : MBBs) { 459 skipNonTerminators(Position, Block); 460 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { 461 assert(Position.Address <= TI->Address && 462 "Addresses shouldn't go forwards"); 463 if (mustRelaxBranch(*TI, Position.Address)) 464 relaxBranch(*TI); 465 skipTerminator(Position, *TI, false); 466 ++TI; 467 } 468 } 469 } 470 471 bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) { 472 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); 473 MF = &F; 474 uint64_t Size = initMBBInfo(); 475 if (Size <= MaxForwardRange || !mustRelaxABranch()) 476 return false; 477 478 setWorstCaseAddresses(); 479 relaxBranches(); 480 return true; 481 } 482 483 FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) { 484 return new SystemZLongBranch(TM); 485 } 486