xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp (revision 5ffd83dbcc34f10e07f6d3e968ae6365869615f4)
1*5ffd83dbSDimitry Andric //===---------- SystemZPhysRegCopy.cpp - Handle phys reg copies -----------===//
2*5ffd83dbSDimitry Andric //
3*5ffd83dbSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*5ffd83dbSDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*5ffd83dbSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*5ffd83dbSDimitry Andric //
7*5ffd83dbSDimitry Andric //===----------------------------------------------------------------------===//
8*5ffd83dbSDimitry Andric //
9*5ffd83dbSDimitry Andric // This pass makes sure that a COPY of a physical register will be
10*5ffd83dbSDimitry Andric // implementable after register allocation in copyPhysReg() (this could be
11*5ffd83dbSDimitry Andric // done in EmitInstrWithCustomInserter() instead if COPY instructions would
12*5ffd83dbSDimitry Andric // be passed to it).
13*5ffd83dbSDimitry Andric //
14*5ffd83dbSDimitry Andric //===----------------------------------------------------------------------===//
15*5ffd83dbSDimitry Andric 
16*5ffd83dbSDimitry Andric #include "SystemZMachineFunctionInfo.h"
17*5ffd83dbSDimitry Andric #include "SystemZTargetMachine.h"
18*5ffd83dbSDimitry Andric #include "llvm/CodeGen/MachineDominators.h"
19*5ffd83dbSDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h"
20*5ffd83dbSDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
21*5ffd83dbSDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
22*5ffd83dbSDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
23*5ffd83dbSDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h"
24*5ffd83dbSDimitry Andric #include "llvm/Target/TargetMachine.h"
25*5ffd83dbSDimitry Andric 
26*5ffd83dbSDimitry Andric using namespace llvm;
27*5ffd83dbSDimitry Andric 
28*5ffd83dbSDimitry Andric #define SYSTEMZ_COPYPHYSREGS_NAME "SystemZ Copy Physregs"
29*5ffd83dbSDimitry Andric 
30*5ffd83dbSDimitry Andric namespace llvm {
31*5ffd83dbSDimitry Andric   void initializeSystemZCopyPhysRegsPass(PassRegistry&);
32*5ffd83dbSDimitry Andric }
33*5ffd83dbSDimitry Andric 
34*5ffd83dbSDimitry Andric namespace {
35*5ffd83dbSDimitry Andric 
36*5ffd83dbSDimitry Andric class SystemZCopyPhysRegs : public MachineFunctionPass {
37*5ffd83dbSDimitry Andric public:
38*5ffd83dbSDimitry Andric   static char ID;
39*5ffd83dbSDimitry Andric   SystemZCopyPhysRegs()
40*5ffd83dbSDimitry Andric     : MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
41*5ffd83dbSDimitry Andric     initializeSystemZCopyPhysRegsPass(*PassRegistry::getPassRegistry());
42*5ffd83dbSDimitry Andric   }
43*5ffd83dbSDimitry Andric 
44*5ffd83dbSDimitry Andric   StringRef getPassName() const override { return SYSTEMZ_COPYPHYSREGS_NAME; }
45*5ffd83dbSDimitry Andric 
46*5ffd83dbSDimitry Andric   bool runOnMachineFunction(MachineFunction &MF) override;
47*5ffd83dbSDimitry Andric   void getAnalysisUsage(AnalysisUsage &AU) const override;
48*5ffd83dbSDimitry Andric 
49*5ffd83dbSDimitry Andric private:
50*5ffd83dbSDimitry Andric 
51*5ffd83dbSDimitry Andric   bool visitMBB(MachineBasicBlock &MBB);
52*5ffd83dbSDimitry Andric 
53*5ffd83dbSDimitry Andric   const SystemZInstrInfo *TII;
54*5ffd83dbSDimitry Andric   MachineRegisterInfo *MRI;
55*5ffd83dbSDimitry Andric };
56*5ffd83dbSDimitry Andric 
57*5ffd83dbSDimitry Andric char SystemZCopyPhysRegs::ID = 0;
58*5ffd83dbSDimitry Andric 
59*5ffd83dbSDimitry Andric } // end anonymous namespace
60*5ffd83dbSDimitry Andric 
61*5ffd83dbSDimitry Andric INITIALIZE_PASS(SystemZCopyPhysRegs, "systemz-copy-physregs",
62*5ffd83dbSDimitry Andric                 SYSTEMZ_COPYPHYSREGS_NAME, false, false)
63*5ffd83dbSDimitry Andric 
64*5ffd83dbSDimitry Andric FunctionPass *llvm::createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM) {
65*5ffd83dbSDimitry Andric   return new SystemZCopyPhysRegs();
66*5ffd83dbSDimitry Andric }
67*5ffd83dbSDimitry Andric 
68*5ffd83dbSDimitry Andric void SystemZCopyPhysRegs::getAnalysisUsage(AnalysisUsage &AU) const {
69*5ffd83dbSDimitry Andric   AU.setPreservesCFG();
70*5ffd83dbSDimitry Andric   MachineFunctionPass::getAnalysisUsage(AU);
71*5ffd83dbSDimitry Andric }
72*5ffd83dbSDimitry Andric 
73*5ffd83dbSDimitry Andric bool SystemZCopyPhysRegs::visitMBB(MachineBasicBlock &MBB) {
74*5ffd83dbSDimitry Andric   bool Modified = false;
75*5ffd83dbSDimitry Andric 
76*5ffd83dbSDimitry Andric   // Certain special registers can only be copied from a subset of the
77*5ffd83dbSDimitry Andric   // default register class of the type. It is therefore necessary to create
78*5ffd83dbSDimitry Andric   // the target copy instructions before regalloc instead of in copyPhysReg().
79*5ffd83dbSDimitry Andric   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
80*5ffd83dbSDimitry Andric        MBBI != E; ) {
81*5ffd83dbSDimitry Andric     MachineInstr *MI = &*MBBI++;
82*5ffd83dbSDimitry Andric     if (!MI->isCopy())
83*5ffd83dbSDimitry Andric       continue;
84*5ffd83dbSDimitry Andric 
85*5ffd83dbSDimitry Andric     DebugLoc DL = MI->getDebugLoc();
86*5ffd83dbSDimitry Andric     Register SrcReg = MI->getOperand(1).getReg();
87*5ffd83dbSDimitry Andric     Register DstReg = MI->getOperand(0).getReg();
88*5ffd83dbSDimitry Andric     if (DstReg.isVirtual() &&
89*5ffd83dbSDimitry Andric         (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
90*5ffd83dbSDimitry Andric       Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
91*5ffd83dbSDimitry Andric       if (SrcReg == SystemZ::CC)
92*5ffd83dbSDimitry Andric         BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp);
93*5ffd83dbSDimitry Andric       else
94*5ffd83dbSDimitry Andric         BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
95*5ffd83dbSDimitry Andric       MI->getOperand(1).setReg(Tmp);
96*5ffd83dbSDimitry Andric       Modified = true;
97*5ffd83dbSDimitry Andric     }
98*5ffd83dbSDimitry Andric     else if (SrcReg.isVirtual() &&
99*5ffd83dbSDimitry Andric              SystemZ::AR32BitRegClass.contains(DstReg)) {
100*5ffd83dbSDimitry Andric       Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
101*5ffd83dbSDimitry Andric       MI->getOperand(0).setReg(Tmp);
102*5ffd83dbSDimitry Andric       BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
103*5ffd83dbSDimitry Andric       Modified = true;
104*5ffd83dbSDimitry Andric     }
105*5ffd83dbSDimitry Andric   }
106*5ffd83dbSDimitry Andric 
107*5ffd83dbSDimitry Andric   return Modified;
108*5ffd83dbSDimitry Andric }
109*5ffd83dbSDimitry Andric 
110*5ffd83dbSDimitry Andric bool SystemZCopyPhysRegs::runOnMachineFunction(MachineFunction &F) {
111*5ffd83dbSDimitry Andric   TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
112*5ffd83dbSDimitry Andric   MRI = &F.getRegInfo();
113*5ffd83dbSDimitry Andric 
114*5ffd83dbSDimitry Andric   bool Modified = false;
115*5ffd83dbSDimitry Andric   for (auto &MBB : F)
116*5ffd83dbSDimitry Andric     Modified |= visitMBB(MBB);
117*5ffd83dbSDimitry Andric 
118*5ffd83dbSDimitry Andric   return Modified;
119*5ffd83dbSDimitry Andric }
120*5ffd83dbSDimitry Andric 
121