1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "SparcTargetMachine.h" 13 #include "LeonPasses.h" 14 #include "Sparc.h" 15 #include "SparcMachineFunctionInfo.h" 16 #include "SparcTargetObjectFile.h" 17 #include "TargetInfo/SparcTargetInfo.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/CodeGen/TargetPassConfig.h" 20 #include "llvm/IR/LegacyPassManager.h" 21 #include "llvm/MC/TargetRegistry.h" 22 #include <optional> 23 using namespace llvm; 24 25 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { 26 // Register the target. 27 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget()); 28 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target()); 29 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); 30 31 PassRegistry &PR = *PassRegistry::getPassRegistry(); 32 initializeSparcDAGToDAGISelPass(PR); 33 } 34 35 static std::string computeDataLayout(const Triple &T, bool is64Bit) { 36 // Sparc is typically big endian, but some are little. 37 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; 38 Ret += "-m:e"; 39 40 // Some ABIs have 32bit pointers. 41 if (!is64Bit) 42 Ret += "-p:32:32"; 43 44 // Alignments for 64 bit integers. 45 Ret += "-i64:64"; 46 47 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. 48 // On SparcV9 registers can hold 64 or 32 bits, on others only 32. 49 if (is64Bit) 50 Ret += "-n32:64"; 51 else 52 Ret += "-f128:64-n32"; 53 54 if (is64Bit) 55 Ret += "-S128"; 56 else 57 Ret += "-S64"; 58 59 return Ret; 60 } 61 62 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { 63 return RM.value_or(Reloc::Static); 64 } 65 66 // Code models. Some only make sense for 64-bit code. 67 // 68 // SunCC Reloc CodeModel Constraints 69 // abs32 Static Small text+data+bss linked below 2^32 bytes 70 // abs44 Static Medium text+data+bss linked below 2^44 bytes 71 // abs64 Static Large text smaller than 2^31 bytes 72 // pic13 PIC_ Small GOT < 2^13 bytes 73 // pic32 PIC_ Medium GOT < 2^32 bytes 74 // 75 // All code models require that the text segment is smaller than 2GB. 76 static CodeModel::Model 77 getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM, 78 bool Is64Bit, bool JIT) { 79 if (CM) { 80 if (*CM == CodeModel::Tiny) 81 report_fatal_error("Target does not support the tiny CodeModel", false); 82 if (*CM == CodeModel::Kernel) 83 report_fatal_error("Target does not support the kernel CodeModel", false); 84 return *CM; 85 } 86 if (Is64Bit) { 87 if (JIT) 88 return CodeModel::Large; 89 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 90 } 91 return CodeModel::Small; 92 } 93 94 /// Create an ILP32 architecture model 95 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, 96 StringRef CPU, StringRef FS, 97 const TargetOptions &Options, 98 std::optional<Reloc::Model> RM, 99 std::optional<CodeModel::Model> CM, 100 CodeGenOpt::Level OL, bool JIT, 101 bool is64bit) 102 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, 103 getEffectiveRelocModel(RM), 104 getEffectiveSparcCodeModel( 105 CM, getEffectiveRelocModel(RM), is64bit, JIT), 106 OL), 107 TLOF(std::make_unique<SparcELFTargetObjectFile>()), 108 Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit), 109 is64Bit(is64bit) { 110 initAsmInfo(); 111 } 112 113 SparcTargetMachine::~SparcTargetMachine() = default; 114 115 const SparcSubtarget * 116 SparcTargetMachine::getSubtargetImpl(const Function &F) const { 117 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 118 Attribute FSAttr = F.getFnAttribute("target-features"); 119 120 std::string CPU = 121 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 122 std::string FS = 123 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 124 125 // FIXME: This is related to the code below to reset the target options, 126 // we need to know whether or not the soft float flag is set on the 127 // function, so we can enable it as a subtarget feature. 128 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 129 130 if (softFloat) 131 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 132 133 auto &I = SubtargetMap[CPU + FS]; 134 if (!I) { 135 // This needs to be done before we create a new subtarget since any 136 // creation will depend on the TM and the code generation flags on the 137 // function that reside in TargetOptions. 138 resetTargetOptions(F); 139 I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this, 140 this->is64Bit); 141 } 142 return I.get(); 143 } 144 145 MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo( 146 BumpPtrAllocator &Allocator, const Function &F, 147 const TargetSubtargetInfo *STI) const { 148 return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator, 149 F, STI); 150 } 151 152 namespace { 153 /// Sparc Code Generator Pass Configuration Options. 154 class SparcPassConfig : public TargetPassConfig { 155 public: 156 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM) 157 : TargetPassConfig(TM, PM) {} 158 159 SparcTargetMachine &getSparcTargetMachine() const { 160 return getTM<SparcTargetMachine>(); 161 } 162 163 void addIRPasses() override; 164 bool addInstSelector() override; 165 void addPreEmitPass() override; 166 }; 167 } // namespace 168 169 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 170 return new SparcPassConfig(*this, PM); 171 } 172 173 void SparcPassConfig::addIRPasses() { 174 addPass(createAtomicExpandPass()); 175 176 TargetPassConfig::addIRPasses(); 177 } 178 179 bool SparcPassConfig::addInstSelector() { 180 addPass(createSparcISelDag(getSparcTargetMachine())); 181 return false; 182 } 183 184 void SparcPassConfig::addPreEmitPass(){ 185 addPass(createSparcDelaySlotFillerPass()); 186 187 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) 188 { 189 addPass(new InsertNOPLoad()); 190 } 191 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) { 192 addPass(new DetectRoundChange()); 193 } 194 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) 195 { 196 addPass(new FixAllFDIVSQRT()); 197 } 198 } 199 200 void SparcV8TargetMachine::anchor() { } 201 202 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, 203 StringRef CPU, StringRef FS, 204 const TargetOptions &Options, 205 std::optional<Reloc::Model> RM, 206 std::optional<CodeModel::Model> CM, 207 CodeGenOpt::Level OL, bool JIT) 208 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 209 210 void SparcV9TargetMachine::anchor() { } 211 212 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, 213 StringRef CPU, StringRef FS, 214 const TargetOptions &Options, 215 std::optional<Reloc::Model> RM, 216 std::optional<CodeModel::Model> CM, 217 CodeGenOpt::Level OL, bool JIT) 218 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 219 220 void SparcelTargetMachine::anchor() {} 221 222 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, 223 StringRef CPU, StringRef FS, 224 const TargetOptions &Options, 225 std::optional<Reloc::Model> RM, 226 std::optional<CodeModel::Model> CM, 227 CodeGenOpt::Level OL, bool JIT) 228 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 229