181ad6265SDimitry Andric//===-- SPIRVRegisterInfo.td - SPIR-V Register defs --------*- tablegen -*-===// 281ad6265SDimitry Andric// 381ad6265SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric// 781ad6265SDimitry Andric//===----------------------------------------------------------------------===// 881ad6265SDimitry Andric// 981ad6265SDimitry Andric// Declarations that describe the SPIR-V register file. 1081ad6265SDimitry Andric// 1181ad6265SDimitry Andric//===----------------------------------------------------------------------===// 1281ad6265SDimitry Andric 1381ad6265SDimitry Andriclet Namespace = "SPIRV" in { 14*0fca6ea1SDimitry Andric // Pointer types for patterns with the GlobalISelEmitter 15*0fca6ea1SDimitry Andric def p32 : PtrValueType <i32, 0>; 16*0fca6ea1SDimitry Andric def p64 : PtrValueType <i64, 0>; 1781ad6265SDimitry Andric 18*0fca6ea1SDimitry Andric class VTPtrVec<int nelem, PtrValueType ptr> 19*0fca6ea1SDimitry Andric : VTVec<nelem, ValueType<ptr.Size, ptr.Value>, ptr.Value> { 20*0fca6ea1SDimitry Andric int isPointer = true; 21*0fca6ea1SDimitry Andric } 22*0fca6ea1SDimitry Andric 23*0fca6ea1SDimitry Andric def v2p32 : VTPtrVec<2, p32>; 24*0fca6ea1SDimitry Andric def v2p64 : VTPtrVec<2, p64>; 25*0fca6ea1SDimitry Andric 26*0fca6ea1SDimitry Andric // Class for type registers 2781ad6265SDimitry Andric def TYPE0 : Register<"TYPE0">; 2881ad6265SDimitry Andric def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>; 2981ad6265SDimitry Andric 30*0fca6ea1SDimitry Andric // Class for non-type registers 3181ad6265SDimitry Andric def ID0 : Register<"ID0">; 32*0fca6ea1SDimitry Andric def ID640 : Register<"ID640">; 33*0fca6ea1SDimitry Andric def fID0 : Register<"fID0">; 34*0fca6ea1SDimitry Andric def fID640 : Register<"fID640">; 35*0fca6ea1SDimitry Andric def pID320 : Register<"pID320">; 36*0fca6ea1SDimitry Andric def pID640 : Register<"pID640">; 37*0fca6ea1SDimitry Andric def vID0 : Register<"vID0">; 38*0fca6ea1SDimitry Andric def vfID0 : Register<"vfID0">; 39*0fca6ea1SDimitry Andric def vpID320 : Register<"vpID320">; 40*0fca6ea1SDimitry Andric def vpID640 : Register<"vpID640">; 4181ad6265SDimitry Andric 42*0fca6ea1SDimitry Andric def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>; 43*0fca6ea1SDimitry Andric def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>; 44*0fca6ea1SDimitry Andric def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>; 45*0fca6ea1SDimitry Andric def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>; 46*0fca6ea1SDimitry Andric def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>; 47*0fca6ea1SDimitry Andric def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>; 48*0fca6ea1SDimitry Andric def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>; 49*0fca6ea1SDimitry Andric def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>; 50*0fca6ea1SDimitry Andric def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>; 51*0fca6ea1SDimitry Andric def vpID64 : RegisterClass<"SPIRV", [v2p64], 32, (add vpID640)>; 52*0fca6ea1SDimitry Andric 53*0fca6ea1SDimitry Andric def ANYID : RegisterClass< 54*0fca6ea1SDimitry Andric "SPIRV", 55*0fca6ea1SDimitry Andric [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64], 56*0fca6ea1SDimitry Andric 32, 57*0fca6ea1SDimitry Andric (add ID0, ID640, fID0, fID640, pID320, pID640, vID0, vfID0, vpID320, vpID640)>; 5881ad6265SDimitry Andric 5981ad6265SDimitry Andric // A few instructions like OpName can take ids from both type and non-type 6081ad6265SDimitry Andric // instructions, so we need a super-class to allow for both to count as valid 6181ad6265SDimitry Andric // arguments for these instructions. 6281ad6265SDimitry Andric def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>; 6381ad6265SDimitry Andric} 64