181ad6265SDimitry Andric //===-- SPIRVInstrInfo.h - SPIR-V Instruction Information -------*- C++ -*-===// 281ad6265SDimitry Andric // 381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric // 781ad6265SDimitry Andric //===----------------------------------------------------------------------===// 881ad6265SDimitry Andric // 981ad6265SDimitry Andric // This file contains the SPIR-V implementation of the TargetInstrInfo class. 1081ad6265SDimitry Andric // 1181ad6265SDimitry Andric //===----------------------------------------------------------------------===// 1281ad6265SDimitry Andric 1381ad6265SDimitry Andric #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVINSTRINFO_H 1481ad6265SDimitry Andric #define LLVM_LIB_TARGET_SPIRV_SPIRVINSTRINFO_H 1581ad6265SDimitry Andric 1681ad6265SDimitry Andric #include "SPIRVRegisterInfo.h" 1781ad6265SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 1881ad6265SDimitry Andric 1981ad6265SDimitry Andric #define GET_INSTRINFO_HEADER 2081ad6265SDimitry Andric #include "SPIRVGenInstrInfo.inc" 2181ad6265SDimitry Andric 2281ad6265SDimitry Andric namespace llvm { 2381ad6265SDimitry Andric 2481ad6265SDimitry Andric class SPIRVInstrInfo : public SPIRVGenInstrInfo { 2581ad6265SDimitry Andric const SPIRVRegisterInfo RI; 2681ad6265SDimitry Andric 2781ad6265SDimitry Andric public: 2881ad6265SDimitry Andric SPIRVInstrInfo(); 2981ad6265SDimitry Andric 3081ad6265SDimitry Andric const SPIRVRegisterInfo &getRegisterInfo() const { return RI; } 3181ad6265SDimitry Andric bool isHeaderInstr(const MachineInstr &MI) const; 3281ad6265SDimitry Andric bool isConstantInstr(const MachineInstr &MI) const; 33*0fca6ea1SDimitry Andric bool isInlineAsmDefInstr(const MachineInstr &MI) const; 3481ad6265SDimitry Andric bool isTypeDeclInstr(const MachineInstr &MI) const; 3581ad6265SDimitry Andric bool isDecorationInstr(const MachineInstr &MI) const; 36bdd1243dSDimitry Andric bool canUseFastMathFlags(const MachineInstr &MI) const; 37bdd1243dSDimitry Andric bool canUseNSW(const MachineInstr &MI) const; 38bdd1243dSDimitry Andric bool canUseNUW(const MachineInstr &MI) const; 3981ad6265SDimitry Andric 4081ad6265SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 4181ad6265SDimitry Andric MachineBasicBlock *&FBB, 4281ad6265SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 4381ad6265SDimitry Andric bool AllowModify = false) const override; 4481ad6265SDimitry Andric 4581ad6265SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 4681ad6265SDimitry Andric int *BytesRemoved = nullptr) const override; 4781ad6265SDimitry Andric 4881ad6265SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 4981ad6265SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 5081ad6265SDimitry Andric const DebugLoc &DL, 5181ad6265SDimitry Andric int *BytesAdded = nullptr) const override; 5281ad6265SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 5381ad6265SDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 5481ad6265SDimitry Andric bool KillSrc) const override; 55fcaf7f86SDimitry Andric bool expandPostRAPseudo(MachineInstr &MI) const override; 5681ad6265SDimitry Andric }; 57*0fca6ea1SDimitry Andric 58*0fca6ea1SDimitry Andric namespace SPIRV { 59*0fca6ea1SDimitry Andric enum AsmComments { 60*0fca6ea1SDimitry Andric // It is a half type 61*0fca6ea1SDimitry Andric ASM_PRINTER_WIDTH16 = MachineInstr::TAsmComments 62*0fca6ea1SDimitry Andric }; 63*0fca6ea1SDimitry Andric } // namespace SPIRV 64*0fca6ea1SDimitry Andric 6581ad6265SDimitry Andric } // namespace llvm 6681ad6265SDimitry Andric 6781ad6265SDimitry Andric #endif // LLVM_LIB_TARGET_SPIRV_SPIRVINSTRINFO_H 68