1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about RISCV target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetMachine.h" 14 #include "MCTargetDesc/RISCVBaseInfo.h" 15 #include "RISCV.h" 16 #include "RISCVMachineFunctionInfo.h" 17 #include "RISCVMacroFusion.h" 18 #include "RISCVTargetObjectFile.h" 19 #include "RISCVTargetTransformInfo.h" 20 #include "TargetInfo/RISCVTargetInfo.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Analysis/TargetTransformInfo.h" 23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 25 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 26 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 27 #include "llvm/CodeGen/MIRParser/MIParser.h" 28 #include "llvm/CodeGen/MIRYamlMapping.h" 29 #include "llvm/CodeGen/Passes.h" 30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 31 #include "llvm/CodeGen/TargetPassConfig.h" 32 #include "llvm/IR/LegacyPassManager.h" 33 #include "llvm/InitializePasses.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/FormattedStream.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Transforms/IPO.h" 38 using namespace llvm; 39 40 static cl::opt<bool> EnableRedundantCopyElimination( 41 "riscv-enable-copyelim", 42 cl::desc("Enable the redundant copy elimination pass"), cl::init(true), 43 cl::Hidden); 44 45 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { 46 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); 47 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); 48 auto *PR = PassRegistry::getPassRegistry(); 49 initializeGlobalISel(*PR); 50 initializeRISCVMakeCompressibleOptPass(*PR); 51 initializeRISCVGatherScatterLoweringPass(*PR); 52 initializeRISCVMergeBaseOffsetOptPass(*PR); 53 initializeRISCVSExtWRemovalPass(*PR); 54 initializeRISCVExpandPseudoPass(*PR); 55 initializeRISCVInsertVSETVLIPass(*PR); 56 } 57 58 static StringRef computeDataLayout(const Triple &TT) { 59 if (TT.isArch64Bit()) 60 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; 61 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); 62 return "e-m:e-p:32:32-i64:64-n32-S128"; 63 } 64 65 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 66 Optional<Reloc::Model> RM) { 67 return RM.value_or(Reloc::Static); 68 } 69 70 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, 71 StringRef CPU, StringRef FS, 72 const TargetOptions &Options, 73 Optional<Reloc::Model> RM, 74 Optional<CodeModel::Model> CM, 75 CodeGenOpt::Level OL, bool JIT) 76 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, 77 getEffectiveRelocModel(TT, RM), 78 getEffectiveCodeModel(CM, CodeModel::Small), OL), 79 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) { 80 initAsmInfo(); 81 82 // RISC-V supports the MachineOutliner. 83 setMachineOutliner(true); 84 setSupportsDefaultOutlining(true); 85 } 86 87 const RISCVSubtarget * 88 RISCVTargetMachine::getSubtargetImpl(const Function &F) const { 89 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 90 Attribute TuneAttr = F.getFnAttribute("tune-cpu"); 91 Attribute FSAttr = F.getFnAttribute("target-features"); 92 93 std::string CPU = 94 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 95 std::string TuneCPU = 96 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; 97 std::string FS = 98 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 99 std::string Key = CPU + TuneCPU + FS; 100 auto &I = SubtargetMap[Key]; 101 if (!I) { 102 // This needs to be done before we create a new subtarget since any 103 // creation will depend on the TM and the code generation flags on the 104 // function that reside in TargetOptions. 105 resetTargetOptions(F); 106 auto ABIName = Options.MCOptions.getABIName(); 107 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>( 108 F.getParent()->getModuleFlag("target-abi"))) { 109 auto TargetABI = RISCVABI::getTargetABI(ABIName); 110 if (TargetABI != RISCVABI::ABI_Unknown && 111 ModuleTargetABI->getString() != ABIName) { 112 report_fatal_error("-target-abi option != target-abi module flag"); 113 } 114 ABIName = ModuleTargetABI->getString(); 115 } 116 I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); 117 } 118 return I.get(); 119 } 120 121 TargetTransformInfo 122 RISCVTargetMachine::getTargetTransformInfo(const Function &F) const { 123 return TargetTransformInfo(RISCVTTIImpl(this, F)); 124 } 125 126 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes 127 // for all memory accesses, so it is reasonable to assume that an 128 // implementation has no-op address space casts. If an implementation makes a 129 // change to this, they can override it here. 130 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, 131 unsigned DstAS) const { 132 return true; 133 } 134 135 namespace { 136 class RISCVPassConfig : public TargetPassConfig { 137 public: 138 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) 139 : TargetPassConfig(TM, PM) {} 140 141 RISCVTargetMachine &getRISCVTargetMachine() const { 142 return getTM<RISCVTargetMachine>(); 143 } 144 145 ScheduleDAGInstrs * 146 createMachineScheduler(MachineSchedContext *C) const override { 147 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); 148 if (ST.hasMacroFusion()) { 149 ScheduleDAGMILive *DAG = createGenericSchedLive(C); 150 DAG->addMutation(createRISCVMacroFusionDAGMutation()); 151 return DAG; 152 } 153 return nullptr; 154 } 155 156 ScheduleDAGInstrs * 157 createPostMachineScheduler(MachineSchedContext *C) const override { 158 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); 159 if (ST.hasMacroFusion()) { 160 ScheduleDAGMI *DAG = createGenericSchedPostRA(C); 161 DAG->addMutation(createRISCVMacroFusionDAGMutation()); 162 return DAG; 163 } 164 return nullptr; 165 } 166 167 void addIRPasses() override; 168 bool addPreISel() override; 169 bool addInstSelector() override; 170 bool addIRTranslator() override; 171 bool addLegalizeMachineIR() override; 172 bool addRegBankSelect() override; 173 bool addGlobalInstructionSelect() override; 174 void addPreEmitPass() override; 175 void addPreEmitPass2() override; 176 void addPreSched2() override; 177 void addMachineSSAOptimization() override; 178 void addPreRegAlloc() override; 179 void addPostRegAlloc() override; 180 }; 181 } // namespace 182 183 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { 184 return new RISCVPassConfig(*this, PM); 185 } 186 187 void RISCVPassConfig::addIRPasses() { 188 addPass(createAtomicExpandPass()); 189 190 addPass(createRISCVGatherScatterLoweringPass()); 191 192 TargetPassConfig::addIRPasses(); 193 } 194 195 bool RISCVPassConfig::addPreISel() { 196 if (TM->getOptLevel() != CodeGenOpt::None) { 197 // Add a barrier before instruction selection so that we will not get 198 // deleted block address after enabling default outlining. See D99707 for 199 // more details. 200 addPass(createBarrierNoopPass()); 201 } 202 return false; 203 } 204 205 bool RISCVPassConfig::addInstSelector() { 206 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel())); 207 208 return false; 209 } 210 211 bool RISCVPassConfig::addIRTranslator() { 212 addPass(new IRTranslator(getOptLevel())); 213 return false; 214 } 215 216 bool RISCVPassConfig::addLegalizeMachineIR() { 217 addPass(new Legalizer()); 218 return false; 219 } 220 221 bool RISCVPassConfig::addRegBankSelect() { 222 addPass(new RegBankSelect()); 223 return false; 224 } 225 226 bool RISCVPassConfig::addGlobalInstructionSelect() { 227 addPass(new InstructionSelect(getOptLevel())); 228 return false; 229 } 230 231 void RISCVPassConfig::addPreSched2() {} 232 233 void RISCVPassConfig::addPreEmitPass() { 234 addPass(&BranchRelaxationPassID); 235 addPass(createRISCVMakeCompressibleOptPass()); 236 } 237 238 void RISCVPassConfig::addPreEmitPass2() { 239 addPass(createRISCVExpandPseudoPass()); 240 // Schedule the expansion of AMOs at the last possible moment, avoiding the 241 // possibility for other passes to break the requirements for forward 242 // progress in the LR/SC block. 243 addPass(createRISCVExpandAtomicPseudoPass()); 244 } 245 246 void RISCVPassConfig::addMachineSSAOptimization() { 247 TargetPassConfig::addMachineSSAOptimization(); 248 249 if (TM->getTargetTriple().getArch() == Triple::riscv64) 250 addPass(createRISCVSExtWRemovalPass()); 251 } 252 253 void RISCVPassConfig::addPreRegAlloc() { 254 if (TM->getOptLevel() != CodeGenOpt::None) 255 addPass(createRISCVMergeBaseOffsetOptPass()); 256 addPass(createRISCVInsertVSETVLIPass()); 257 } 258 259 void RISCVPassConfig::addPostRegAlloc() { 260 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) 261 addPass(createRISCVRedundantCopyEliminationPass()); 262 } 263 264 yaml::MachineFunctionInfo * 265 RISCVTargetMachine::createDefaultFuncInfoYAML() const { 266 return new yaml::RISCVMachineFunctionInfo(); 267 } 268 269 yaml::MachineFunctionInfo * 270 RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const { 271 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>(); 272 return new yaml::RISCVMachineFunctionInfo(*MFI); 273 } 274 275 bool RISCVTargetMachine::parseMachineFunctionInfo( 276 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS, 277 SMDiagnostic &Error, SMRange &SourceRange) const { 278 const auto &YamlMFI = 279 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI); 280 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI); 281 return false; 282 } 283