1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about RISCV target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetMachine.h" 14 #include "MCTargetDesc/RISCVBaseInfo.h" 15 #include "RISCV.h" 16 #include "RISCVTargetObjectFile.h" 17 #include "RISCVTargetTransformInfo.h" 18 #include "TargetInfo/RISCVTargetInfo.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 22 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 23 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 24 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 25 #include "llvm/CodeGen/Passes.h" 26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 27 #include "llvm/CodeGen/TargetPassConfig.h" 28 #include "llvm/IR/LegacyPassManager.h" 29 #include "llvm/InitializePasses.h" 30 #include "llvm/MC/TargetRegistry.h" 31 #include "llvm/Support/FormattedStream.h" 32 #include "llvm/Target/TargetOptions.h" 33 using namespace llvm; 34 35 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { 36 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); 37 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); 38 auto *PR = PassRegistry::getPassRegistry(); 39 initializeGlobalISel(*PR); 40 initializeRISCVGatherScatterLoweringPass(*PR); 41 initializeRISCVMergeBaseOffsetOptPass(*PR); 42 initializeRISCVExpandPseudoPass(*PR); 43 initializeRISCVInsertVSETVLIPass(*PR); 44 } 45 46 static StringRef computeDataLayout(const Triple &TT) { 47 if (TT.isArch64Bit()) 48 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; 49 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); 50 return "e-m:e-p:32:32-i64:64-n32-S128"; 51 } 52 53 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 54 Optional<Reloc::Model> RM) { 55 if (!RM.hasValue()) 56 return Reloc::Static; 57 return *RM; 58 } 59 60 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, 61 StringRef CPU, StringRef FS, 62 const TargetOptions &Options, 63 Optional<Reloc::Model> RM, 64 Optional<CodeModel::Model> CM, 65 CodeGenOpt::Level OL, bool JIT) 66 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, 67 getEffectiveRelocModel(TT, RM), 68 getEffectiveCodeModel(CM, CodeModel::Small), OL), 69 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) { 70 initAsmInfo(); 71 72 // RISC-V supports the MachineOutliner. 73 setMachineOutliner(true); 74 } 75 76 const RISCVSubtarget * 77 RISCVTargetMachine::getSubtargetImpl(const Function &F) const { 78 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 79 Attribute TuneAttr = F.getFnAttribute("tune-cpu"); 80 Attribute FSAttr = F.getFnAttribute("target-features"); 81 82 std::string CPU = 83 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 84 std::string TuneCPU = 85 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; 86 std::string FS = 87 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 88 std::string Key = CPU + TuneCPU + FS; 89 auto &I = SubtargetMap[Key]; 90 if (!I) { 91 // This needs to be done before we create a new subtarget since any 92 // creation will depend on the TM and the code generation flags on the 93 // function that reside in TargetOptions. 94 resetTargetOptions(F); 95 auto ABIName = Options.MCOptions.getABIName(); 96 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>( 97 F.getParent()->getModuleFlag("target-abi"))) { 98 auto TargetABI = RISCVABI::getTargetABI(ABIName); 99 if (TargetABI != RISCVABI::ABI_Unknown && 100 ModuleTargetABI->getString() != ABIName) { 101 report_fatal_error("-target-abi option != target-abi module flag"); 102 } 103 ABIName = ModuleTargetABI->getString(); 104 } 105 I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); 106 } 107 return I.get(); 108 } 109 110 TargetTransformInfo 111 RISCVTargetMachine::getTargetTransformInfo(const Function &F) { 112 return TargetTransformInfo(RISCVTTIImpl(this, F)); 113 } 114 115 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes 116 // for all memory accesses, so it is reasonable to assume that an 117 // implementation has no-op address space casts. If an implementation makes a 118 // change to this, they can override it here. 119 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, 120 unsigned DstAS) const { 121 return true; 122 } 123 124 namespace { 125 class RISCVPassConfig : public TargetPassConfig { 126 public: 127 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) 128 : TargetPassConfig(TM, PM) {} 129 130 RISCVTargetMachine &getRISCVTargetMachine() const { 131 return getTM<RISCVTargetMachine>(); 132 } 133 134 void addIRPasses() override; 135 bool addInstSelector() override; 136 bool addIRTranslator() override; 137 bool addLegalizeMachineIR() override; 138 bool addRegBankSelect() override; 139 bool addGlobalInstructionSelect() override; 140 void addPreEmitPass() override; 141 void addPreEmitPass2() override; 142 void addPreSched2() override; 143 void addPreRegAlloc() override; 144 }; 145 } // namespace 146 147 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { 148 return new RISCVPassConfig(*this, PM); 149 } 150 151 void RISCVPassConfig::addIRPasses() { 152 addPass(createAtomicExpandPass()); 153 154 addPass(createRISCVGatherScatterLoweringPass()); 155 156 TargetPassConfig::addIRPasses(); 157 } 158 159 bool RISCVPassConfig::addInstSelector() { 160 addPass(createRISCVISelDag(getRISCVTargetMachine())); 161 162 return false; 163 } 164 165 bool RISCVPassConfig::addIRTranslator() { 166 addPass(new IRTranslator(getOptLevel())); 167 return false; 168 } 169 170 bool RISCVPassConfig::addLegalizeMachineIR() { 171 addPass(new Legalizer()); 172 return false; 173 } 174 175 bool RISCVPassConfig::addRegBankSelect() { 176 addPass(new RegBankSelect()); 177 return false; 178 } 179 180 bool RISCVPassConfig::addGlobalInstructionSelect() { 181 addPass(new InstructionSelect(getOptLevel())); 182 return false; 183 } 184 185 void RISCVPassConfig::addPreSched2() {} 186 187 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } 188 189 void RISCVPassConfig::addPreEmitPass2() { 190 addPass(createRISCVExpandPseudoPass()); 191 // Schedule the expansion of AMOs at the last possible moment, avoiding the 192 // possibility for other passes to break the requirements for forward 193 // progress in the LR/SC block. 194 addPass(createRISCVExpandAtomicPseudoPass()); 195 } 196 197 void RISCVPassConfig::addPreRegAlloc() { 198 if (TM->getOptLevel() != CodeGenOpt::None) 199 addPass(createRISCVMergeBaseOffsetOptPass()); 200 addPass(createRISCVInsertVSETVLIPass()); 201 } 202