1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 15 16 #include "MCTargetDesc/RISCVBaseInfo.h" 17 #include "RISCVFrameLowering.h" 18 #include "RISCVISelLowering.h" 19 #include "RISCVInstrInfo.h" 20 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 25 #include "llvm/CodeGen/TargetSubtargetInfo.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/Target/TargetMachine.h" 28 29 #define GET_SUBTARGETINFO_HEADER 30 #include "RISCVGenSubtargetInfo.inc" 31 32 namespace llvm { 33 class StringRef; 34 35 class RISCVSubtarget : public RISCVGenSubtargetInfo { 36 virtual void anchor(); 37 bool HasStdExtM = false; 38 bool HasStdExtA = false; 39 bool HasStdExtF = false; 40 bool HasStdExtD = false; 41 bool HasStdExtC = false; 42 bool HasStdExtZba = false; 43 bool HasStdExtZbb = false; 44 bool HasStdExtZbc = false; 45 bool HasStdExtZbe = false; 46 bool HasStdExtZbf = false; 47 bool HasStdExtZbm = false; 48 bool HasStdExtZbp = false; 49 bool HasStdExtZbr = false; 50 bool HasStdExtZbs = false; 51 bool HasStdExtZbt = false; 52 bool HasStdExtV = false; 53 bool HasStdExtZvlsseg = false; 54 bool HasStdExtZvamo = false; 55 bool HasStdExtZfhmin = false; 56 bool HasStdExtZfh = false; 57 bool HasRV64 = false; 58 bool IsRV32E = false; 59 bool EnableLinkerRelax = false; 60 bool EnableRVCHintInstrs = true; 61 bool EnableSaveRestore = false; 62 unsigned XLen = 32; 63 MVT XLenVT = MVT::i32; 64 uint8_t MaxInterleaveFactor = 2; 65 RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; 66 BitVector UserReservedRegister; 67 RISCVFrameLowering FrameLowering; 68 RISCVInstrInfo InstrInfo; 69 RISCVRegisterInfo RegInfo; 70 RISCVTargetLowering TLInfo; 71 SelectionDAGTargetInfo TSInfo; 72 73 /// Initializes using the passed in CPU and feature strings so that we can 74 /// use initializer lists for subtarget initialization. 75 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT, 76 StringRef CPU, 77 StringRef TuneCPU, 78 StringRef FS, 79 StringRef ABIName); 80 81 public: 82 // Initializes the data members to match that of the specified triple. 83 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, 84 StringRef FS, StringRef ABIName, const TargetMachine &TM); 85 86 // Parses features string setting specified subtarget options. The 87 // definition of this function is auto-generated by tblgen. 88 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 89 90 const RISCVFrameLowering *getFrameLowering() const override { 91 return &FrameLowering; 92 } 93 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } 94 const RISCVRegisterInfo *getRegisterInfo() const override { 95 return &RegInfo; 96 } 97 const RISCVTargetLowering *getTargetLowering() const override { 98 return &TLInfo; 99 } 100 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 101 return &TSInfo; 102 } 103 bool enableMachineScheduler() const override { return true; } 104 bool hasStdExtM() const { return HasStdExtM; } 105 bool hasStdExtA() const { return HasStdExtA; } 106 bool hasStdExtF() const { return HasStdExtF; } 107 bool hasStdExtD() const { return HasStdExtD; } 108 bool hasStdExtC() const { return HasStdExtC; } 109 bool hasStdExtZba() const { return HasStdExtZba; } 110 bool hasStdExtZbb() const { return HasStdExtZbb; } 111 bool hasStdExtZbc() const { return HasStdExtZbc; } 112 bool hasStdExtZbe() const { return HasStdExtZbe; } 113 bool hasStdExtZbf() const { return HasStdExtZbf; } 114 bool hasStdExtZbm() const { return HasStdExtZbm; } 115 bool hasStdExtZbp() const { return HasStdExtZbp; } 116 bool hasStdExtZbr() const { return HasStdExtZbr; } 117 bool hasStdExtZbs() const { return HasStdExtZbs; } 118 bool hasStdExtZbt() const { return HasStdExtZbt; } 119 bool hasStdExtV() const { return HasStdExtV; } 120 bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } 121 bool hasStdExtZvamo() const { return HasStdExtZvamo; } 122 bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } 123 bool hasStdExtZfh() const { return HasStdExtZfh; } 124 bool is64Bit() const { return HasRV64; } 125 bool isRV32E() const { return IsRV32E; } 126 bool enableLinkerRelax() const { return EnableLinkerRelax; } 127 bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } 128 bool enableSaveRestore() const { return EnableSaveRestore; } 129 MVT getXLenVT() const { return XLenVT; } 130 unsigned getXLen() const { return XLen; } 131 RISCVABI::ABI getTargetABI() const { return TargetABI; } 132 bool isRegisterReservedByUser(Register i) const { 133 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); 134 return UserReservedRegister[i]; 135 } 136 137 // Vector codegen related methods. 138 bool hasVInstructions() const { return HasStdExtV; } 139 bool hasVInstructionsI64() const { return HasStdExtV; } 140 bool hasVInstructionsF16() const { return HasStdExtV && hasStdExtZfh(); } 141 bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); } 142 bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); } 143 // F16 and F64 both require F32. 144 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } 145 unsigned getMaxInterleaveFactor() const { 146 return hasVInstructions() ? MaxInterleaveFactor : 1; 147 } 148 149 protected: 150 // GlobalISel related APIs. 151 std::unique_ptr<CallLowering> CallLoweringInfo; 152 std::unique_ptr<InstructionSelector> InstSelector; 153 std::unique_ptr<LegalizerInfo> Legalizer; 154 std::unique_ptr<RegisterBankInfo> RegBankInfo; 155 156 public: 157 const CallLowering *getCallLowering() const override; 158 InstructionSelector *getInstructionSelector() const override; 159 const LegalizerInfo *getLegalizerInfo() const override; 160 const RegisterBankInfo *getRegBankInfo() const override; 161 162 // Return the known range for the bit length of RVV data registers. A value 163 // of 0 means nothing is known about that particular limit beyond what's 164 // implied by the architecture. 165 unsigned getMaxRVVVectorSizeInBits() const; 166 unsigned getMinRVVVectorSizeInBits() const; 167 unsigned getMaxLMULForFixedLengthVectors() const; 168 unsigned getMaxELENForFixedLengthVectors() const; 169 bool useRVVForFixedLengthVectors() const; 170 }; 171 } // End llvm namespace 172 173 #endif 174