1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVSubtarget.h" 14 #include "RISCV.h" 15 #include "RISCVCallLowering.h" 16 #include "RISCVFrameLowering.h" 17 #include "RISCVLegalizerInfo.h" 18 #include "RISCVRegisterBankInfo.h" 19 #include "RISCVTargetMachine.h" 20 #include "llvm/MC/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "riscv-subtarget" 25 26 #define GET_SUBTARGETINFO_TARGET_DESC 27 #define GET_SUBTARGETINFO_CTOR 28 #include "RISCVGenSubtargetInfo.inc" 29 30 static cl::opt<unsigned> RVVVectorBitsMax( 31 "riscv-v-vector-bits-max", 32 cl::desc("Assume V extension vector registers are at most this big, " 33 "with zero meaning no maximum size is assumed."), 34 cl::init(0), cl::Hidden); 35 36 static cl::opt<unsigned> RVVVectorBitsMin( 37 "riscv-v-vector-bits-min", 38 cl::desc("Assume V extension vector registers are at least this big, " 39 "with zero meaning no minimum size is assumed."), 40 cl::init(0), cl::Hidden); 41 42 static cl::opt<unsigned> RVVVectorLMULMax( 43 "riscv-v-fixed-length-vector-lmul-max", 44 cl::desc("The maximum LMUL value to use for fixed length vectors. " 45 "Fractional LMUL values are not supported."), 46 cl::init(8), cl::Hidden); 47 48 static cl::opt<unsigned> RVVVectorELENMax( 49 "riscv-v-fixed-length-vector-elen-max", 50 cl::desc("The maximum ELEN value to use for fixed length vectors."), 51 cl::init(64), cl::Hidden); 52 53 void RISCVSubtarget::anchor() {} 54 55 RISCVSubtarget & 56 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, 57 StringRef TuneCPU, StringRef FS, 58 StringRef ABIName) { 59 // Determine default and user-specified characteristics 60 bool Is64Bit = TT.isArch64Bit(); 61 if (CPU.empty()) 62 CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; 63 if (CPU == "generic") 64 report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + 65 (Is64Bit ? "generic-rv64" : "generic-rv32")); 66 67 if (TuneCPU.empty()) 68 TuneCPU = CPU; 69 70 ParseSubtargetFeatures(CPU, TuneCPU, FS); 71 if (Is64Bit) { 72 XLenVT = MVT::i64; 73 XLen = 64; 74 } 75 76 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); 77 RISCVFeatures::validate(TT, getFeatureBits()); 78 return *this; 79 } 80 81 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, 82 StringRef TuneCPU, StringRef FS, 83 StringRef ABIName, const TargetMachine &TM) 84 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), 85 UserReservedRegister(RISCV::NUM_TARGET_REGS), 86 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), 87 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { 88 CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); 89 Legalizer.reset(new RISCVLegalizerInfo(*this)); 90 91 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); 92 RegBankInfo.reset(RBI); 93 InstSelector.reset(createRISCVInstructionSelector( 94 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); 95 } 96 97 const CallLowering *RISCVSubtarget::getCallLowering() const { 98 return CallLoweringInfo.get(); 99 } 100 101 InstructionSelector *RISCVSubtarget::getInstructionSelector() const { 102 return InstSelector.get(); 103 } 104 105 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { 106 return Legalizer.get(); 107 } 108 109 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { 110 return RegBankInfo.get(); 111 } 112 113 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { 114 assert(hasVInstructions() && 115 "Tried to get vector length without Zve or V extension support!"); 116 if (RVVVectorBitsMax == 0) 117 return 0; 118 assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 && 119 isPowerOf2_32(RVVVectorBitsMax) && 120 "V extension requires vector length to be in the range of 128 to " 121 "65536 and a power of 2!"); 122 assert(RVVVectorBitsMax >= RVVVectorBitsMin && 123 "Minimum V extension vector length should not be larger than its " 124 "maximum!"); 125 unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax); 126 return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max); 127 } 128 129 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { 130 assert(hasVInstructions() && 131 "Tried to get vector length without Zve or V extension support!"); 132 assert((RVVVectorBitsMin == 0 || 133 (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 && 134 isPowerOf2_32(RVVVectorBitsMin))) && 135 "V extension requires vector length to be in the range of 128 to " 136 "65536 and a power of 2!"); 137 assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) && 138 "Minimum V extension vector length should not be larger than its " 139 "maximum!"); 140 unsigned Min = RVVVectorBitsMin; 141 if (RVVVectorBitsMax != 0) 142 Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax); 143 return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min); 144 } 145 146 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const { 147 assert(hasVInstructions() && 148 "Tried to get vector length without Zve or V extension support!"); 149 assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) && 150 "V extension requires a LMUL to be at most 8 and a power of 2!"); 151 return PowerOf2Floor( 152 std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1)); 153 } 154 155 unsigned RISCVSubtarget::getMaxELENForFixedLengthVectors() const { 156 assert(hasVInstructions() && 157 "Tried to get maximum ELEN without Zve or V extension support!"); 158 assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 && 159 isPowerOf2_32(RVVVectorELENMax) && 160 "V extension requires a ELEN to be a power of 2 between 8 and 64!"); 161 return PowerOf2Floor( 162 std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, 64), 8)); 163 } 164 165 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { 166 return hasVInstructions() && getMinRVVVectorSizeInBits() != 0; 167 } 168