1*0fca6ea1SDimitry Andric//=== RISCVScheduleZvk.td - RISC-V Scheduling Definitions Zvk -*- tablegen ===// 2*0fca6ea1SDimitry Andric// 3*0fca6ea1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0fca6ea1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0fca6ea1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0fca6ea1SDimitry Andric// 7*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 8*0fca6ea1SDimitry Andric 9*0fca6ea1SDimitry Andric/// Define scheduler resources associated with def operands. 10*0fca6ea1SDimitry Andric 11*0fca6ea1SDimitry Andric/// Zvbb extension 12*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVBREVV">; 13*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVCLZV">; 14*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVCPOPV">; 15*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVCTZV">; 16*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVWSLLV">; 17*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVWSLLX">; 18*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVWSLLI">; 19*0fca6ea1SDimitry Andric 20*0fca6ea1SDimitry Andric/// Zvbc extension 21*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVCLMULV">; 22*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVCLMULX">; 23*0fca6ea1SDimitry Andric 24*0fca6ea1SDimitry Andric/// Zvkb extension 25*0fca6ea1SDimitry Andric// VANDN uses WriteVIALU[V|X|I] 26*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVBREV8V">; 27*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVREV8V">; 28*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVRotV">; 29*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVRotX">; 30*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVRotI">; 31*0fca6ea1SDimitry Andric 32*0fca6ea1SDimitry Andric/// Zvkg extension 33*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVGHSHV">; 34*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVGMULV">; 35*0fca6ea1SDimitry Andric 36*0fca6ea1SDimitry Andric/// Zvknha or Zvknhb extensions 37*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSHA2CHV">; 38*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSHA2CLV">; 39*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSHA2MSV">; 40*0fca6ea1SDimitry Andric 41*0fca6ea1SDimitry Andric/// Zvkned extension 42*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVAESMVV">; 43*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVAESKF1V">; 44*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVAESKF2V">; 45*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVAESZV">; 46*0fca6ea1SDimitry Andric 47*0fca6ea1SDimitry Andric/// Zvksed extension 48*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSM4KV">; 49*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSM4RV">; 50*0fca6ea1SDimitry Andric 51*0fca6ea1SDimitry Andric/// Zvksh extension 52*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSM3CV">; 53*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVSM3MEV">; 54*0fca6ea1SDimitry Andric 55*0fca6ea1SDimitry Andric/// Define scheduler resources associated with use operands. 56*0fca6ea1SDimitry Andric/// Zvbb extension 57*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVBREVV">; 58*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVCLZV">; 59*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVCPOPV">; 60*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVCTZV">; 61*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVWSLLV">; 62*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVWSLLX">; 63*0fca6ea1SDimitry Andric 64*0fca6ea1SDimitry Andric/// Zvbc extension 65*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVCLMULV">; 66*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVCLMULX">; 67*0fca6ea1SDimitry Andric 68*0fca6ea1SDimitry Andric/// Zvkb extension 69*0fca6ea1SDimitry Andric// VANDN uses ReadVIALU[V|X|I] 70*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVBREV8V">; 71*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVREV8V">; 72*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVRotV">; 73*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVRotX">; 74*0fca6ea1SDimitry Andric 75*0fca6ea1SDimitry Andric/// Zvkg extension 76*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVGHSHV">; 77*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVGMULV">; 78*0fca6ea1SDimitry Andric 79*0fca6ea1SDimitry Andric/// Zvknha or Zvknhb extensions 80*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSHA2CHV">; 81*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSHA2CLV">; 82*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSHA2MSV">; 83*0fca6ea1SDimitry Andric 84*0fca6ea1SDimitry Andric/// Zvkned extension 85*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVAESMVV">; 86*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVAESKF1V">; 87*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVAESKF2V">; 88*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVAESZV">; 89*0fca6ea1SDimitry Andric 90*0fca6ea1SDimitry Andric/// Zvksed extension 91*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSM4KV">; 92*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSM4RV">; 93*0fca6ea1SDimitry Andric 94*0fca6ea1SDimitry Andric/// Zvksh extension 95*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSM3CV">; 96*0fca6ea1SDimitry Andricdefm "" : LMULSchedReads<"ReadVSM3MEV">; 97*0fca6ea1SDimitry Andric 98*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvbb { 99*0fca6ea1SDimitry Andriclet Unsupported = true in { 100*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVBREVV", []>; 101*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVCLZV", []>; 102*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVCPOPV", []>; 103*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVCTZV", []>; 104*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVWSLLV", []>; 105*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVWSLLX", []>; 106*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVWSLLI", []>; 107*0fca6ea1SDimitry Andric 108*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVBREVV", 0>; 109*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVCLZV", 0>; 110*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVCPOPV", 0>; 111*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVCTZV", 0>; 112*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVWSLLV", 0>; 113*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVWSLLX", 0>; 114*0fca6ea1SDimitry Andric} 115*0fca6ea1SDimitry Andric} 116*0fca6ea1SDimitry Andric 117*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvbc { 118*0fca6ea1SDimitry Andriclet Unsupported = true in { 119*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVCLMULV", []>; 120*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVCLMULX", []>; 121*0fca6ea1SDimitry Andric 122*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVCLMULV", 0>; 123*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVCLMULX", 0>; 124*0fca6ea1SDimitry Andric} 125*0fca6ea1SDimitry Andric} 126*0fca6ea1SDimitry Andric 127*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvkb { 128*0fca6ea1SDimitry Andriclet Unsupported = true in { 129*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVBREV8V", []>; 130*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVREV8V", []>; 131*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVRotV", []>; 132*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVRotX", []>; 133*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVRotI", []>; 134*0fca6ea1SDimitry Andric 135*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVBREV8V", 0>; 136*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVREV8V", 0>; 137*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVRotV", 0>; 138*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVRotX", 0>; 139*0fca6ea1SDimitry Andric} 140*0fca6ea1SDimitry Andric} 141*0fca6ea1SDimitry Andric 142*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvkg { 143*0fca6ea1SDimitry Andriclet Unsupported = true in { 144*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVGHSHV", []>; 145*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVGMULV", []>; 146*0fca6ea1SDimitry Andric 147*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVGHSHV", 0>; 148*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVGMULV", 0>; 149*0fca6ea1SDimitry Andric} 150*0fca6ea1SDimitry Andric} 151*0fca6ea1SDimitry Andric 152*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvknhaOrZvknhb { 153*0fca6ea1SDimitry Andriclet Unsupported = true in { 154*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSHA2CHV", []>; 155*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSHA2CLV", []>; 156*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSHA2MSV", []>; 157*0fca6ea1SDimitry Andric 158*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; 159*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; 160*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; 161*0fca6ea1SDimitry Andric} 162*0fca6ea1SDimitry Andric} 163*0fca6ea1SDimitry Andric 164*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvkned { 165*0fca6ea1SDimitry Andriclet Unsupported = true in { 166*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVAESMVV", []>; 167*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVAESKF1V", []>; 168*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVAESKF2V", []>; 169*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVAESZV", []>; 170*0fca6ea1SDimitry Andric 171*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVAESMVV", 0>; 172*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; 173*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVAESKF2V", 0>; 174*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVAESZV", 0>; 175*0fca6ea1SDimitry Andric} 176*0fca6ea1SDimitry Andric} 177*0fca6ea1SDimitry Andric 178*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvksed { 179*0fca6ea1SDimitry Andriclet Unsupported = true in { 180*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSM4KV", []>; 181*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSM4RV", []>; 182*0fca6ea1SDimitry Andric 183*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSM4KV", 0>; 184*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSM4RV", 0>; 185*0fca6ea1SDimitry Andric} 186*0fca6ea1SDimitry Andric} 187*0fca6ea1SDimitry Andric 188*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvksh { 189*0fca6ea1SDimitry Andriclet Unsupported = true in { 190*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSM3CV", []>; 191*0fca6ea1SDimitry Andricdefm "" : LMULWriteRes<"WriteVSM3MEV", []>; 192*0fca6ea1SDimitry Andric 193*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSM3CV", 0>; 194*0fca6ea1SDimitry Andricdefm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; 195*0fca6ea1SDimitry Andric} 196*0fca6ea1SDimitry Andric} 197*0fca6ea1SDimitry Andric 198*0fca6ea1SDimitry Andric// Helper class to define all RISC-V Vector Crypto extensions as unsupported 199*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZvk { 200*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvbb; 201*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvbc; 202*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvkb; 203*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvkg; 204*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvknhaOrZvknhb; 205*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvkned; 206*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvksed; 207*0fca6ea1SDimitry Andricdefm "" : UnsupportedSchedZvksh; 208*0fca6ea1SDimitry Andric} 209