1*0fca6ea1SDimitry Andric//===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===// 2*0fca6ea1SDimitry Andric// 3*0fca6ea1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0fca6ea1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0fca6ea1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0fca6ea1SDimitry Andric// 7*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 8*0fca6ea1SDimitry Andric// 9*0fca6ea1SDimitry Andric// This file describes the scheduling information for SiFive extensions. 10*0fca6ea1SDimitry Andric// 11*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 12*0fca6ea1SDimitry Andric 13*0fca6ea1SDimitry Andricmulticlass LMULSchedWritesVCIX<string id>{ 14*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVC_" # id>; 15*0fca6ea1SDimitry Andricdefm "" : LMULSchedWrites<"WriteVC_V_" # id>; 16*0fca6ea1SDimitry Andric} 17*0fca6ea1SDimitry Andric 18*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"I">; 19*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"X">; 20*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"IV">; 21*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"VV">; 22*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"XV">; 23*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"IVV">; 24*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"IVW">; 25*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"VVV">; 26*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"VVW">; 27*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"XVV">; 28*0fca6ea1SDimitry Andricdefm "" : LMULSchedWritesVCIX<"XVW">; 29*0fca6ea1SDimitry Andricforeach f = ["FPR16", "FPR32", "FPR64"] in { 30*0fca6ea1SDimitry Andric defm "" : LMULSchedWritesVCIX<f # "V">; 31*0fca6ea1SDimitry Andric defm "" : LMULSchedWritesVCIX<f # "VV">; 32*0fca6ea1SDimitry Andric defm "" : LMULSchedWritesVCIX<f # "VW">; 33*0fca6ea1SDimitry Andric} 34*0fca6ea1SDimitry Andric 35*0fca6ea1SDimitry Andricmulticlass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{ 36*0fca6ea1SDimitry Andricdefm : LMULWriteRes<"WriteVC_" # id, resources>; 37*0fca6ea1SDimitry Andricdefm : LMULWriteRes<"WriteVC_V_" # id, resources>; 38*0fca6ea1SDimitry Andric} 39*0fca6ea1SDimitry Andric 40*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedXsfvcp { 41*0fca6ea1SDimitry Andriclet Unsupported = true in { 42*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"I", []>; 43*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"X", []>; 44*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"IV", []>; 45*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"VV", []>; 46*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"XV", []>; 47*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"IVV", []>; 48*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"IVW", []>; 49*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"VVV", []>; 50*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"VVW", []>; 51*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"XVV", []>; 52*0fca6ea1SDimitry Andricdefm : LMULWriteResVCIX<"XVW", []>; 53*0fca6ea1SDimitry Andricforeach f = ["FPR16", "FPR32", "FPR64"] in { 54*0fca6ea1SDimitry Andric defm : LMULWriteResVCIX<f # "V", []>; 55*0fca6ea1SDimitry Andric defm : LMULWriteResVCIX<f # "VV", []>; 56*0fca6ea1SDimitry Andric defm : LMULWriteResVCIX<f # "VW", []>; 57*0fca6ea1SDimitry Andric} 58*0fca6ea1SDimitry Andric} 59*0fca6ea1SDimitry Andric} 60