1//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// RISC-V processors supported. 11//===----------------------------------------------------------------------===// 12 13class RISCVTuneInfo { 14 bits<8> PrefFunctionAlignment = 1; 15 bits<8> PrefLoopAlignment = 1; 16 17 // Information needed by LoopDataPrefetch. 18 bits<16> CacheLineSize = 0; 19 bits<16> PrefetchDistance = 0; 20 bits<16> MinPrefetchStride = 1; 21 bits<32> MaxPrefetchIterationsAhead = -1; 22 23 bits<32> MinimumJumpTableEntries = 5; 24} 25 26def RISCVTuneInfoTable : GenericTable { 27 let FilterClass = "RISCVTuneInfo"; 28 let CppTypeName = "RISCVTuneInfo"; 29 let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment", 30 "CacheLineSize", "PrefetchDistance", 31 "MinPrefetchStride", "MaxPrefetchIterationsAhead", 32 "MinimumJumpTableEntries"]; 33} 34 35def getRISCVTuneInfo : SearchIndex { 36 let Table = RISCVTuneInfoTable; 37 let Key = ["Name"]; 38} 39 40class GenericTuneInfo: RISCVTuneInfo; 41 42class RISCVProcessorModel<string n, 43 SchedMachineModel m, 44 list<SubtargetFeature> f, 45 list<SubtargetFeature> tunef = [], 46 string default_march = ""> 47 : ProcessorModel<n, m, f, tunef> { 48 string DefaultMarch = default_march; 49} 50 51class RISCVTuneProcessorModel<string n, 52 SchedMachineModel m, 53 list<SubtargetFeature> tunef = [], 54 list<SubtargetFeature> f = []> 55 : ProcessorModel<n, m, f,tunef>; 56 57def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", 58 NoSchedModel, 59 [Feature32Bit]>, 60 GenericTuneInfo; 61def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", 62 NoSchedModel, 63 [Feature64Bit]>, 64 GenericTuneInfo; 65// Support generic for compatibility with other targets. The triple will be used 66// to change to the appropriate rv32/rv64 version. 67def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo; 68 69def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", 70 RocketModel, 71 [Feature32Bit, 72 FeatureStdExtZifencei, 73 FeatureStdExtZicsr]>; 74def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", 75 RocketModel, 76 [Feature64Bit, 77 FeatureStdExtZifencei, 78 FeatureStdExtZicsr]>; 79def ROCKET : RISCVTuneProcessorModel<"rocket", 80 RocketModel>; 81 82def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", 83 SiFive7Model, 84 [TuneSiFive7]>; 85 86def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20", 87 RocketModel, 88 [Feature32Bit, 89 FeatureStdExtZicsr, 90 FeatureStdExtZifencei, 91 FeatureStdExtM, 92 FeatureStdExtC]>; 93 94def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21", 95 RocketModel, 96 [Feature32Bit, 97 FeatureStdExtZicsr, 98 FeatureStdExtZifencei, 99 FeatureStdExtM, 100 FeatureStdExtA, 101 FeatureStdExtC]>; 102 103def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24", 104 RocketModel, 105 [Feature32Bit, 106 FeatureStdExtZifencei, 107 FeatureStdExtM, 108 FeatureStdExtA, 109 FeatureStdExtF, 110 FeatureStdExtC]>; 111 112def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31", 113 RocketModel, 114 [Feature32Bit, 115 FeatureStdExtZifencei, 116 FeatureStdExtZicsr, 117 FeatureStdExtM, 118 FeatureStdExtA, 119 FeatureStdExtC]>; 120 121def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34", 122 RocketModel, 123 [Feature32Bit, 124 FeatureStdExtZifencei, 125 FeatureStdExtM, 126 FeatureStdExtA, 127 FeatureStdExtF, 128 FeatureStdExtC]>; 129 130def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76", 131 SiFive7Model, 132 [Feature32Bit, 133 FeatureStdExtZifencei, 134 FeatureStdExtM, 135 FeatureStdExtA, 136 FeatureStdExtF, 137 FeatureStdExtC], 138 [TuneSiFive7]>; 139 140def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21", 141 RocketModel, 142 [Feature64Bit, 143 FeatureStdExtZicsr, 144 FeatureStdExtZifencei, 145 FeatureStdExtM, 146 FeatureStdExtA, 147 FeatureStdExtC]>; 148 149def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51", 150 RocketModel, 151 [Feature64Bit, 152 FeatureStdExtZicsr, 153 FeatureStdExtZifencei, 154 FeatureStdExtM, 155 FeatureStdExtA, 156 FeatureStdExtC]>; 157 158def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54", 159 RocketModel, 160 [Feature64Bit, 161 FeatureStdExtZifencei, 162 FeatureStdExtM, 163 FeatureStdExtA, 164 FeatureStdExtF, 165 FeatureStdExtD, 166 FeatureStdExtC]>; 167 168def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76", 169 SiFive7Model, 170 [Feature64Bit, 171 FeatureStdExtZifencei, 172 FeatureStdExtM, 173 FeatureStdExtA, 174 FeatureStdExtF, 175 FeatureStdExtD, 176 FeatureStdExtC, 177 FeatureStdExtZihintpause], 178 [TuneSiFive7]>; 179 180def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", 181 RocketModel, 182 [Feature64Bit, 183 FeatureStdExtZifencei, 184 FeatureStdExtM, 185 FeatureStdExtA, 186 FeatureStdExtF, 187 FeatureStdExtD, 188 FeatureStdExtC]>; 189 190def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", 191 SiFive7Model, 192 [Feature64Bit, 193 FeatureStdExtZifencei, 194 FeatureStdExtM, 195 FeatureStdExtA, 196 FeatureStdExtF, 197 FeatureStdExtD, 198 FeatureStdExtC], 199 [TuneSiFive7]>; 200 201def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, 202 [Feature64Bit, 203 FeatureStdExtZifencei, 204 FeatureStdExtM, 205 FeatureStdExtA, 206 FeatureStdExtF, 207 FeatureStdExtD, 208 FeatureStdExtC, 209 FeatureStdExtV, 210 FeatureStdExtZvl512b, 211 FeatureStdExtZfh, 212 FeatureStdExtZvfh, 213 FeatureStdExtZba, 214 FeatureStdExtZbb], 215 [TuneSiFive7, 216 TuneDLenFactor2]>; 217 218def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, 219 [Feature64Bit, 220 FeatureStdExtZifencei, 221 FeatureStdExtM, 222 FeatureStdExtA, 223 FeatureStdExtF, 224 FeatureStdExtD, 225 FeatureStdExtC, 226 FeatureStdExtZicbop, 227 FeatureStdExtZicbom, 228 FeatureStdExtZicboz, 229 FeatureStdExtZihintntl, 230 FeatureStdExtZihintpause, 231 FeatureStdExtZihpm, 232 FeatureStdExtZba, 233 FeatureStdExtZbb, 234 FeatureStdExtZbs, 235 FeatureStdExtZfhmin], 236 [TuneConditionalCompressedMoveFusion]>; 237 238def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", 239 SyntacoreSCR1Model, 240 [Feature32Bit, 241 FeatureStdExtZicsr, 242 FeatureStdExtZifencei, 243 FeatureStdExtC], 244 [TuneNoDefaultUnroll]>; 245 246def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", 247 SyntacoreSCR1Model, 248 [Feature32Bit, 249 FeatureStdExtZicsr, 250 FeatureStdExtZifencei, 251 FeatureStdExtM, 252 FeatureStdExtC], 253 [TuneNoDefaultUnroll]>; 254 255def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", 256 NoSchedModel, 257 [Feature64Bit, 258 FeatureStdExtZifencei, 259 FeatureStdExtZicsr, 260 FeatureStdExtZicntr, 261 FeatureStdExtZihpm, 262 FeatureStdExtZihintpause, 263 FeatureStdExtM, 264 FeatureStdExtA, 265 FeatureStdExtF, 266 FeatureStdExtD, 267 FeatureStdExtC, 268 FeatureStdExtZba, 269 FeatureStdExtZbb, 270 FeatureStdExtZbc, 271 FeatureStdExtZbs, 272 FeatureStdExtZicbom, 273 FeatureStdExtZicbop, 274 FeatureStdExtZicboz, 275 FeatureVendorXVentanaCondOps], 276 [TuneVentanaVeyron, 277 TuneLUIADDIFusion, 278 TuneAUIPCADDIFusion, 279 TuneZExtHFusion, 280 TuneZExtWFusion, 281 TuneShiftedZExtWFusion, 282 TuneLDADDFusion]>; 283 284def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", 285 NoSchedModel, 286 [Feature64Bit, 287 FeatureStdExtZicsr, 288 FeatureStdExtZifencei, 289 FeatureStdExtM, 290 FeatureStdExtA, 291 FeatureStdExtF, 292 FeatureStdExtD, 293 FeatureStdExtC, 294 FeatureStdExtZba, 295 FeatureStdExtZbb, 296 FeatureStdExtZbc, 297 FeatureStdExtZbs, 298 FeatureStdExtZkn, 299 FeatureStdExtZksed, 300 FeatureStdExtZksh, 301 FeatureStdExtSvinval, 302 FeatureStdExtZicbom, 303 FeatureStdExtZicboz]>; 304