1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of TargetFrameLowering class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVFrameLowering.h" 14 #include "RISCVMachineFunctionInfo.h" 15 #include "RISCVSubtarget.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/RegisterScavenging.h" 21 #include "llvm/IR/DiagnosticInfo.h" 22 #include "llvm/MC/MCDwarf.h" 23 24 using namespace llvm; 25 26 // For now we use x18, a.k.a s2, as pointer to shadow call stack. 27 // User should explicitly set -ffixed-x18 and not use x18 in their asm. 28 static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, 29 MachineBasicBlock::iterator MI, 30 const DebugLoc &DL) { 31 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) 32 return; 33 34 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); 35 Register RAReg = STI.getRegisterInfo()->getRARegister(); 36 37 // Do not save RA to the SCS if it's not saved to the regular stack, 38 // i.e. RA is not at risk of being overwritten. 39 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo(); 40 if (std::none_of(CSI.begin(), CSI.end(), 41 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) 42 return; 43 44 Register SCSPReg = RISCVABI::getSCSPReg(); 45 46 auto &Ctx = MF.getFunction().getContext(); 47 if (!STI.isRegisterReservedByUser(SCSPReg)) { 48 Ctx.diagnose(DiagnosticInfoUnsupported{ 49 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); 50 return; 51 } 52 53 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 54 if (RVFI->useSaveRestoreLibCalls(MF)) { 55 Ctx.diagnose(DiagnosticInfoUnsupported{ 56 MF.getFunction(), 57 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); 58 return; 59 } 60 61 const RISCVInstrInfo *TII = STI.getInstrInfo(); 62 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); 63 int64_t SlotSize = STI.getXLen() / 8; 64 // Store return address to shadow call stack 65 // s[w|d] ra, 0(s2) 66 // addi s2, s2, [4|8] 67 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) 68 .addReg(RAReg) 69 .addReg(SCSPReg) 70 .addImm(0) 71 .setMIFlag(MachineInstr::FrameSetup); 72 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) 73 .addReg(SCSPReg, RegState::Define) 74 .addReg(SCSPReg) 75 .addImm(SlotSize) 76 .setMIFlag(MachineInstr::FrameSetup); 77 } 78 79 static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator MI, 81 const DebugLoc &DL) { 82 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) 83 return; 84 85 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); 86 Register RAReg = STI.getRegisterInfo()->getRARegister(); 87 88 // See emitSCSPrologue() above. 89 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo(); 90 if (std::none_of(CSI.begin(), CSI.end(), 91 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) 92 return; 93 94 Register SCSPReg = RISCVABI::getSCSPReg(); 95 96 auto &Ctx = MF.getFunction().getContext(); 97 if (!STI.isRegisterReservedByUser(SCSPReg)) { 98 Ctx.diagnose(DiagnosticInfoUnsupported{ 99 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); 100 return; 101 } 102 103 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 104 if (RVFI->useSaveRestoreLibCalls(MF)) { 105 Ctx.diagnose(DiagnosticInfoUnsupported{ 106 MF.getFunction(), 107 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); 108 return; 109 } 110 111 const RISCVInstrInfo *TII = STI.getInstrInfo(); 112 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); 113 int64_t SlotSize = STI.getXLen() / 8; 114 // Load return address from shadow call stack 115 // l[w|d] ra, -[4|8](s2) 116 // addi s2, s2, -[4|8] 117 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) 118 .addReg(RAReg, RegState::Define) 119 .addReg(SCSPReg) 120 .addImm(-SlotSize) 121 .setMIFlag(MachineInstr::FrameDestroy); 122 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) 123 .addReg(SCSPReg, RegState::Define) 124 .addReg(SCSPReg) 125 .addImm(-SlotSize) 126 .setMIFlag(MachineInstr::FrameDestroy); 127 } 128 129 // Get the ID of the libcall used for spilling and restoring callee saved 130 // registers. The ID is representative of the number of registers saved or 131 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a 132 // single register. 133 static int getLibCallID(const MachineFunction &MF, 134 const std::vector<CalleeSavedInfo> &CSI) { 135 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 136 137 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) 138 return -1; 139 140 Register MaxReg = RISCV::NoRegister; 141 for (auto &CS : CSI) 142 // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to 143 // registers which can be saved by libcall. 144 if (CS.getFrameIdx() < 0) 145 MaxReg = std::max(MaxReg.id(), CS.getReg().id()); 146 147 if (MaxReg == RISCV::NoRegister) 148 return -1; 149 150 switch (MaxReg) { 151 default: 152 llvm_unreachable("Something has gone wrong!"); 153 case /*s11*/ RISCV::X27: return 12; 154 case /*s10*/ RISCV::X26: return 11; 155 case /*s9*/ RISCV::X25: return 10; 156 case /*s8*/ RISCV::X24: return 9; 157 case /*s7*/ RISCV::X23: return 8; 158 case /*s6*/ RISCV::X22: return 7; 159 case /*s5*/ RISCV::X21: return 6; 160 case /*s4*/ RISCV::X20: return 5; 161 case /*s3*/ RISCV::X19: return 4; 162 case /*s2*/ RISCV::X18: return 3; 163 case /*s1*/ RISCV::X9: return 2; 164 case /*s0*/ RISCV::X8: return 1; 165 case /*ra*/ RISCV::X1: return 0; 166 } 167 } 168 169 // Get the name of the libcall used for spilling callee saved registers. 170 // If this function will not use save/restore libcalls, then return a nullptr. 171 static const char * 172 getSpillLibCallName(const MachineFunction &MF, 173 const std::vector<CalleeSavedInfo> &CSI) { 174 static const char *const SpillLibCalls[] = { 175 "__riscv_save_0", 176 "__riscv_save_1", 177 "__riscv_save_2", 178 "__riscv_save_3", 179 "__riscv_save_4", 180 "__riscv_save_5", 181 "__riscv_save_6", 182 "__riscv_save_7", 183 "__riscv_save_8", 184 "__riscv_save_9", 185 "__riscv_save_10", 186 "__riscv_save_11", 187 "__riscv_save_12" 188 }; 189 190 int LibCallID = getLibCallID(MF, CSI); 191 if (LibCallID == -1) 192 return nullptr; 193 return SpillLibCalls[LibCallID]; 194 } 195 196 // Get the name of the libcall used for restoring callee saved registers. 197 // If this function will not use save/restore libcalls, then return a nullptr. 198 static const char * 199 getRestoreLibCallName(const MachineFunction &MF, 200 const std::vector<CalleeSavedInfo> &CSI) { 201 static const char *const RestoreLibCalls[] = { 202 "__riscv_restore_0", 203 "__riscv_restore_1", 204 "__riscv_restore_2", 205 "__riscv_restore_3", 206 "__riscv_restore_4", 207 "__riscv_restore_5", 208 "__riscv_restore_6", 209 "__riscv_restore_7", 210 "__riscv_restore_8", 211 "__riscv_restore_9", 212 "__riscv_restore_10", 213 "__riscv_restore_11", 214 "__riscv_restore_12" 215 }; 216 217 int LibCallID = getLibCallID(MF, CSI); 218 if (LibCallID == -1) 219 return nullptr; 220 return RestoreLibCalls[LibCallID]; 221 } 222 223 // Return true if the specified function should have a dedicated frame 224 // pointer register. This is true if frame pointer elimination is 225 // disabled, if it needs dynamic stack realignment, if the function has 226 // variable sized allocas, or if the frame address is taken. 227 bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { 228 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 229 230 const MachineFrameInfo &MFI = MF.getFrameInfo(); 231 return MF.getTarget().Options.DisableFramePointerElim(MF) || 232 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || 233 MFI.isFrameAddressTaken(); 234 } 235 236 bool RISCVFrameLowering::hasBP(const MachineFunction &MF) const { 237 const MachineFrameInfo &MFI = MF.getFrameInfo(); 238 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 239 240 // If we do not reserve stack space for outgoing arguments in prologue, 241 // we will adjust the stack pointer before call instruction. After the 242 // adjustment, we can not use SP to access the stack objects for the 243 // arguments. Instead, use BP to access these stack objects. 244 return (MFI.hasVarSizedObjects() || 245 (!hasReservedCallFrame(MF) && (!MFI.isMaxCallFrameSizeComputed() || 246 MFI.getMaxCallFrameSize() != 0))) && 247 TRI->hasStackRealignment(MF); 248 } 249 250 // Determines the size of the frame and maximum call frame size. 251 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const { 252 MachineFrameInfo &MFI = MF.getFrameInfo(); 253 254 // Get the number of bytes to allocate from the FrameInfo. 255 uint64_t FrameSize = MFI.getStackSize(); 256 257 // Get the alignment. 258 Align StackAlign = getStackAlign(); 259 260 // Make sure the frame is aligned. 261 FrameSize = alignTo(FrameSize, StackAlign); 262 263 // Update frame info. 264 MFI.setStackSize(FrameSize); 265 } 266 267 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, 268 MachineBasicBlock::iterator MBBI, 269 const DebugLoc &DL, Register DestReg, 270 Register SrcReg, int64_t Val, 271 MachineInstr::MIFlag Flag) const { 272 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 273 const RISCVInstrInfo *TII = STI.getInstrInfo(); 274 275 if (DestReg == SrcReg && Val == 0) 276 return; 277 278 if (isInt<12>(Val)) { 279 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg) 280 .addReg(SrcReg) 281 .addImm(Val) 282 .setMIFlag(Flag); 283 } else { 284 unsigned Opc = RISCV::ADD; 285 bool isSub = Val < 0; 286 if (isSub) { 287 Val = -Val; 288 Opc = RISCV::SUB; 289 } 290 291 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 292 TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); 293 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) 294 .addReg(SrcReg) 295 .addReg(ScratchReg, RegState::Kill) 296 .setMIFlag(Flag); 297 } 298 } 299 300 // Returns the register used to hold the frame pointer. 301 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } 302 303 // Returns the register used to hold the stack pointer. 304 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } 305 306 static SmallVector<CalleeSavedInfo, 8> 307 getNonLibcallCSI(const MachineFunction &MF, 308 const std::vector<CalleeSavedInfo> &CSI) { 309 const MachineFrameInfo &MFI = MF.getFrameInfo(); 310 SmallVector<CalleeSavedInfo, 8> NonLibcallCSI; 311 312 for (auto &CS : CSI) { 313 int FI = CS.getFrameIdx(); 314 if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default) 315 NonLibcallCSI.push_back(CS); 316 } 317 318 return NonLibcallCSI; 319 } 320 321 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF, 322 MachineBasicBlock &MBB, 323 MachineBasicBlock::iterator MBBI, 324 const DebugLoc &DL, int64_t Amount, 325 MachineInstr::MIFlag Flag) const { 326 assert(Amount != 0 && "Did not need to adjust stack pointer for RVV."); 327 328 const RISCVInstrInfo *TII = STI.getInstrInfo(); 329 Register SPReg = getSPReg(STI); 330 unsigned Opc = RISCV::ADD; 331 if (Amount < 0) { 332 Amount = -Amount; 333 Opc = RISCV::SUB; 334 } 335 // 1. Multiply the number of v-slots to the length of registers 336 Register FactorRegister = 337 TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount, Flag); 338 // 2. SP = SP - RVV stack size 339 BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg) 340 .addReg(SPReg) 341 .addReg(FactorRegister, RegState::Kill) 342 .setMIFlag(Flag); 343 } 344 345 void RISCVFrameLowering::emitPrologue(MachineFunction &MF, 346 MachineBasicBlock &MBB) const { 347 MachineFrameInfo &MFI = MF.getFrameInfo(); 348 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 349 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); 350 const RISCVInstrInfo *TII = STI.getInstrInfo(); 351 MachineBasicBlock::iterator MBBI = MBB.begin(); 352 353 Register FPReg = getFPReg(STI); 354 Register SPReg = getSPReg(STI); 355 Register BPReg = RISCVABI::getBPReg(); 356 357 // Debug location must be unknown since the first debug location is used 358 // to determine the end of the prologue. 359 DebugLoc DL; 360 361 // All calls are tail calls in GHC calling conv, and functions have no 362 // prologue/epilogue. 363 if (MF.getFunction().getCallingConv() == CallingConv::GHC) 364 return; 365 366 // Emit prologue for shadow call stack. 367 emitSCSPrologue(MF, MBB, MBBI, DL); 368 369 // Since spillCalleeSavedRegisters may have inserted a libcall, skip past 370 // any instructions marked as FrameSetup 371 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) 372 ++MBBI; 373 374 // Determine the correct frame layout 375 determineFrameLayout(MF); 376 377 // If libcalls are used to spill and restore callee-saved registers, the frame 378 // has two sections; the opaque section managed by the libcalls, and the 379 // section managed by MachineFrameInfo which can also hold callee saved 380 // registers in fixed stack slots, both of which have negative frame indices. 381 // This gets even more complicated when incoming arguments are passed via the 382 // stack, as these too have negative frame indices. An example is detailed 383 // below: 384 // 385 // | incoming arg | <- FI[-3] 386 // | libcallspill | 387 // | calleespill | <- FI[-2] 388 // | calleespill | <- FI[-1] 389 // | this_frame | <- FI[0] 390 // 391 // For negative frame indices, the offset from the frame pointer will differ 392 // depending on which of these groups the frame index applies to. 393 // The following calculates the correct offset knowing the number of callee 394 // saved registers spilt by the two methods. 395 if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { 396 // Calculate the size of the frame managed by the libcall. The libcalls are 397 // implemented such that the stack will always be 16 byte aligned. 398 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16); 399 RVFI->setLibCallStackSize(LibCallFrameSize); 400 } 401 402 // FIXME (note copied from Lanai): This appears to be overallocating. Needs 403 // investigation. Get the number of bytes to allocate from the FrameInfo. 404 uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding(); 405 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); 406 uint64_t RVVStackSize = RVFI->getRVVStackSize(); 407 408 // Early exit if there is no need to allocate on the stack 409 if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0) 410 return; 411 412 // If the stack pointer has been marked as reserved, then produce an error if 413 // the frame requires stack allocation 414 if (STI.isRegisterReservedByUser(SPReg)) 415 MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{ 416 MF.getFunction(), "Stack pointer required, but has been reserved."}); 417 418 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); 419 // Split the SP adjustment to reduce the offsets of callee saved spill. 420 if (FirstSPAdjustAmount) { 421 StackSize = FirstSPAdjustAmount; 422 RealStackSize = FirstSPAdjustAmount; 423 } 424 425 // Allocate space on the stack if necessary. 426 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); 427 428 // Emit ".cfi_def_cfa_offset RealStackSize" 429 unsigned CFIIndex = MF.addFrameInst( 430 MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize)); 431 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 432 .addCFIIndex(CFIIndex) 433 .setMIFlag(MachineInstr::FrameSetup); 434 435 const auto &CSI = MFI.getCalleeSavedInfo(); 436 437 // The frame pointer is callee-saved, and code has been generated for us to 438 // save it to the stack. We need to skip over the storing of callee-saved 439 // registers as the frame pointer must be modified after it has been saved 440 // to the stack, not before. 441 // FIXME: assumes exactly one instruction is used to save each callee-saved 442 // register. 443 std::advance(MBBI, getNonLibcallCSI(MF, CSI).size()); 444 445 // Iterate over list of callee-saved registers and emit .cfi_offset 446 // directives. 447 for (const auto &Entry : CSI) { 448 int FrameIdx = Entry.getFrameIdx(); 449 int64_t Offset; 450 // Offsets for objects with fixed locations (IE: those saved by libcall) are 451 // simply calculated from the frame index. 452 if (FrameIdx < 0) 453 Offset = FrameIdx * (int64_t) STI.getXLen() / 8; 454 else 455 Offset = MFI.getObjectOffset(Entry.getFrameIdx()) - 456 RVFI->getLibCallStackSize(); 457 Register Reg = Entry.getReg(); 458 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( 459 nullptr, RI->getDwarfRegNum(Reg, true), Offset)); 460 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 461 .addCFIIndex(CFIIndex) 462 .setMIFlag(MachineInstr::FrameSetup); 463 } 464 465 // Generate new FP. 466 if (hasFP(MF)) { 467 if (STI.isRegisterReservedByUser(FPReg)) 468 MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{ 469 MF.getFunction(), "Frame pointer required, but has been reserved."}); 470 471 adjustReg(MBB, MBBI, DL, FPReg, SPReg, 472 RealStackSize - RVFI->getVarArgsSaveSize(), 473 MachineInstr::FrameSetup); 474 475 // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()" 476 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( 477 nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); 478 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 479 .addCFIIndex(CFIIndex) 480 .setMIFlag(MachineInstr::FrameSetup); 481 } 482 483 // Emit the second SP adjustment after saving callee saved registers. 484 if (FirstSPAdjustAmount) { 485 uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; 486 assert(SecondSPAdjustAmount > 0 && 487 "SecondSPAdjustAmount should be greater than zero"); 488 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, 489 MachineInstr::FrameSetup); 490 491 // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0", 492 // don't emit an sp-based .cfi_def_cfa_offset 493 if (!hasFP(MF)) { 494 // Emit ".cfi_def_cfa_offset StackSize" 495 unsigned CFIIndex = MF.addFrameInst( 496 MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize())); 497 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 498 .addCFIIndex(CFIIndex) 499 .setMIFlag(MachineInstr::FrameSetup); 500 } 501 } 502 503 if (RVVStackSize) 504 adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize, 505 MachineInstr::FrameSetup); 506 507 if (hasFP(MF)) { 508 // Realign Stack 509 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); 510 if (RI->hasStackRealignment(MF)) { 511 Align MaxAlignment = MFI.getMaxAlign(); 512 513 const RISCVInstrInfo *TII = STI.getInstrInfo(); 514 if (isInt<12>(-(int)MaxAlignment.value())) { 515 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) 516 .addReg(SPReg) 517 .addImm(-(int)MaxAlignment.value()) 518 .setMIFlag(MachineInstr::FrameSetup); 519 } else { 520 unsigned ShiftAmount = Log2(MaxAlignment); 521 Register VR = 522 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); 523 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) 524 .addReg(SPReg) 525 .addImm(ShiftAmount) 526 .setMIFlag(MachineInstr::FrameSetup); 527 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) 528 .addReg(VR) 529 .addImm(ShiftAmount) 530 .setMIFlag(MachineInstr::FrameSetup); 531 } 532 // FP will be used to restore the frame in the epilogue, so we need 533 // another base register BP to record SP after re-alignment. SP will 534 // track the current stack after allocating variable sized objects. 535 if (hasBP(MF)) { 536 // move BP, SP 537 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg) 538 .addReg(SPReg) 539 .addImm(0) 540 .setMIFlag(MachineInstr::FrameSetup); 541 } 542 } 543 } 544 } 545 546 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, 547 MachineBasicBlock &MBB) const { 548 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); 549 MachineFrameInfo &MFI = MF.getFrameInfo(); 550 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 551 Register FPReg = getFPReg(STI); 552 Register SPReg = getSPReg(STI); 553 554 // All calls are tail calls in GHC calling conv, and functions have no 555 // prologue/epilogue. 556 if (MF.getFunction().getCallingConv() == CallingConv::GHC) 557 return; 558 559 // Get the insert location for the epilogue. If there were no terminators in 560 // the block, get the last instruction. 561 MachineBasicBlock::iterator MBBI = MBB.end(); 562 DebugLoc DL; 563 if (!MBB.empty()) { 564 MBBI = MBB.getFirstTerminator(); 565 if (MBBI == MBB.end()) 566 MBBI = MBB.getLastNonDebugInstr(); 567 DL = MBBI->getDebugLoc(); 568 569 // If this is not a terminator, the actual insert location should be after the 570 // last instruction. 571 if (!MBBI->isTerminator()) 572 MBBI = std::next(MBBI); 573 574 // If callee-saved registers are saved via libcall, place stack adjustment 575 // before this call. 576 while (MBBI != MBB.begin() && 577 std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy)) 578 --MBBI; 579 } 580 581 const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo()); 582 583 // Skip to before the restores of callee-saved registers 584 // FIXME: assumes exactly one instruction is used to restore each 585 // callee-saved register. 586 auto LastFrameDestroy = MBBI; 587 if (!CSI.empty()) 588 LastFrameDestroy = std::prev(MBBI, CSI.size()); 589 590 uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding(); 591 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); 592 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize(); 593 uint64_t RVVStackSize = RVFI->getRVVStackSize(); 594 595 // Restore the stack pointer using the value of the frame pointer. Only 596 // necessary if the stack pointer was modified, meaning the stack size is 597 // unknown. 598 if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects()) { 599 assert(hasFP(MF) && "frame pointer should not have been eliminated"); 600 adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, 601 MachineInstr::FrameDestroy); 602 } else { 603 if (RVVStackSize) 604 adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize, 605 MachineInstr::FrameDestroy); 606 } 607 608 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); 609 if (FirstSPAdjustAmount) { 610 uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; 611 assert(SecondSPAdjustAmount > 0 && 612 "SecondSPAdjustAmount should be greater than zero"); 613 614 adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount, 615 MachineInstr::FrameDestroy); 616 } 617 618 if (FirstSPAdjustAmount) 619 StackSize = FirstSPAdjustAmount; 620 621 // Deallocate stack 622 adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); 623 624 // Emit epilogue for shadow call stack. 625 emitSCSEpilogue(MF, MBB, MBBI, DL); 626 } 627 628 StackOffset 629 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 630 Register &FrameReg) const { 631 const MachineFrameInfo &MFI = MF.getFrameInfo(); 632 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 633 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 634 635 // Callee-saved registers should be referenced relative to the stack 636 // pointer (positive offset), otherwise use the frame pointer (negative 637 // offset). 638 const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo()); 639 int MinCSFI = 0; 640 int MaxCSFI = -1; 641 StackOffset Offset; 642 auto StackID = MFI.getStackID(FI); 643 644 assert((StackID == TargetStackID::Default || 645 StackID == TargetStackID::ScalableVector) && 646 "Unexpected stack ID for the frame object."); 647 if (StackID == TargetStackID::Default) { 648 Offset = 649 StackOffset::getFixed(MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + 650 MFI.getOffsetAdjustment()); 651 } else if (StackID == TargetStackID::ScalableVector) { 652 Offset = StackOffset::getScalable(MFI.getObjectOffset(FI)); 653 } 654 655 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); 656 657 if (CSI.size()) { 658 MinCSFI = CSI[0].getFrameIdx(); 659 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 660 } 661 662 if (FI >= MinCSFI && FI <= MaxCSFI) { 663 FrameReg = RISCV::X2; 664 665 if (FirstSPAdjustAmount) 666 Offset += StackOffset::getFixed(FirstSPAdjustAmount); 667 else 668 Offset += 669 StackOffset::getFixed(MFI.getStackSize() + RVFI->getRVVPadding()); 670 } else if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) { 671 // If the stack was realigned, the frame pointer is set in order to allow 672 // SP to be restored, so we need another base register to record the stack 673 // after realignment. 674 if (hasBP(MF)) { 675 FrameReg = RISCVABI::getBPReg(); 676 // |--------------------------| -- <-- FP 677 // | callee-saved registers | | <----. 678 // |--------------------------| -- | 679 // | realignment (the size of | | | 680 // | this area is not counted | | | 681 // | in MFI.getStackSize()) | | | 682 // |--------------------------| -- | 683 // | Padding after RVV | | | 684 // | (not counted in | | | 685 // | MFI.getStackSize()) | | | 686 // |--------------------------| -- |-- MFI.getStackSize() 687 // | RVV objects | | | 688 // | (not counted in | | | 689 // | MFI.getStackSize()) | | | 690 // |--------------------------| -- | 691 // | Padding before RVV | | | 692 // | (not counted in | | | 693 // | MFI.getStackSize()) | | | 694 // |--------------------------| -- | 695 // | scalar local variables | | <----' 696 // |--------------------------| -- <-- BP 697 // | VarSize objects | | 698 // |--------------------------| -- <-- SP 699 } else { 700 FrameReg = RISCV::X2; 701 // |--------------------------| -- <-- FP 702 // | callee-saved registers | | <----. 703 // |--------------------------| -- | 704 // | realignment (the size of | | | 705 // | this area is not counted | | | 706 // | in MFI.getStackSize()) | | | 707 // |--------------------------| -- | 708 // | Padding after RVV | | | 709 // | (not counted in | | | 710 // | MFI.getStackSize()) | | | 711 // |--------------------------| -- |-- MFI.getStackSize() 712 // | RVV objects | | | 713 // | (not counted in | | | 714 // | MFI.getStackSize()) | | | 715 // |--------------------------| -- | 716 // | Padding before RVV | | | 717 // | (not counted in | | | 718 // | MFI.getStackSize()) | | | 719 // |--------------------------| -- | 720 // | scalar local variables | | <----' 721 // |--------------------------| -- <-- SP 722 } 723 // The total amount of padding surrounding RVV objects is described by 724 // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV 725 // objects to 8 bytes. 726 if (MFI.getStackID(FI) == TargetStackID::Default) { 727 Offset += StackOffset::getFixed(MFI.getStackSize()); 728 if (FI < 0) 729 Offset += StackOffset::getFixed(RVFI->getLibCallStackSize()); 730 } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) { 731 Offset += StackOffset::get( 732 alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8), 733 RVFI->getRVVStackSize()); 734 } 735 } else { 736 FrameReg = RI->getFrameRegister(MF); 737 if (hasFP(MF)) { 738 Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize()); 739 if (FI >= 0) 740 Offset -= StackOffset::getFixed(RVFI->getLibCallStackSize()); 741 // When using FP to access scalable vector objects, we need to minus 742 // the frame size. 743 // 744 // |--------------------------| -- <-- FP 745 // | callee-saved registers | | 746 // |--------------------------| | MFI.getStackSize() 747 // | scalar local variables | | 748 // |--------------------------| -- (Offset of RVV objects is from here.) 749 // | RVV objects | 750 // |--------------------------| 751 // | VarSize objects | 752 // |--------------------------| <-- SP 753 if (MFI.getStackID(FI) == TargetStackID::ScalableVector) 754 Offset -= StackOffset::getFixed(MFI.getStackSize()); 755 } else { 756 // When using SP to access frame objects, we need to add RVV stack size. 757 // 758 // |--------------------------| -- <-- FP 759 // | callee-saved registers | | <----. 760 // |--------------------------| -- | 761 // | Padding after RVV | | | 762 // | (not counted in | | | 763 // | MFI.getStackSize()) | | | 764 // |--------------------------| -- | 765 // | RVV objects | | |-- MFI.getStackSize() 766 // | (not counted in | | | 767 // | MFI.getStackSize()) | | | 768 // |--------------------------| -- | 769 // | Padding before RVV | | | 770 // | (not counted in | | | 771 // | MFI.getStackSize()) | | | 772 // |--------------------------| -- | 773 // | scalar local variables | | <----' 774 // |--------------------------| -- <-- SP 775 // 776 // The total amount of padding surrounding RVV objects is described by 777 // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV 778 // objects to 8 bytes. 779 if (MFI.getStackID(FI) == TargetStackID::Default) { 780 if (MFI.isFixedObjectIndex(FI)) { 781 Offset += 782 StackOffset::get(MFI.getStackSize() + RVFI->getRVVPadding() + 783 RVFI->getLibCallStackSize(), 784 RVFI->getRVVStackSize()); 785 } else { 786 Offset += StackOffset::getFixed(MFI.getStackSize()); 787 } 788 } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) { 789 Offset += StackOffset::get( 790 alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8), 791 RVFI->getRVVStackSize()); 792 } 793 } 794 } 795 796 return Offset; 797 } 798 799 void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, 800 BitVector &SavedRegs, 801 RegScavenger *RS) const { 802 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 803 // Unconditionally spill RA and FP only if the function uses a frame 804 // pointer. 805 if (hasFP(MF)) { 806 SavedRegs.set(RISCV::X1); 807 SavedRegs.set(RISCV::X8); 808 } 809 // Mark BP as used if function has dedicated base pointer. 810 if (hasBP(MF)) 811 SavedRegs.set(RISCVABI::getBPReg()); 812 813 // If interrupt is enabled and there are calls in the handler, 814 // unconditionally save all Caller-saved registers and 815 // all FP registers, regardless whether they are used. 816 MachineFrameInfo &MFI = MF.getFrameInfo(); 817 818 if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) { 819 820 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ 821 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ 822 RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */ 823 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, 824 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */ 825 }; 826 827 for (unsigned i = 0; CSRegs[i]; ++i) 828 SavedRegs.set(CSRegs[i]); 829 830 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) { 831 832 // If interrupt is enabled, this list contains all FP registers. 833 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); 834 835 for (unsigned i = 0; Regs[i]; ++i) 836 if (RISCV::FPR16RegClass.contains(Regs[i]) || 837 RISCV::FPR32RegClass.contains(Regs[i]) || 838 RISCV::FPR64RegClass.contains(Regs[i])) 839 SavedRegs.set(Regs[i]); 840 } 841 } 842 } 843 844 int64_t 845 RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFrameInfo &MFI) const { 846 int64_t Offset = 0; 847 // Create a buffer of RVV objects to allocate. 848 SmallVector<int, 8> ObjectsToAllocate; 849 for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) { 850 unsigned StackID = MFI.getStackID(I); 851 if (StackID != TargetStackID::ScalableVector) 852 continue; 853 if (MFI.isDeadObjectIndex(I)) 854 continue; 855 856 ObjectsToAllocate.push_back(I); 857 } 858 859 // Allocate all RVV locals and spills 860 for (int FI : ObjectsToAllocate) { 861 // ObjectSize in bytes. 862 int64_t ObjectSize = MFI.getObjectSize(FI); 863 // If the data type is the fractional vector type, reserve one vector 864 // register for it. 865 if (ObjectSize < 8) 866 ObjectSize = 8; 867 // Currently, all scalable vector types are aligned to 8 bytes. 868 Offset = alignTo(Offset + ObjectSize, 8); 869 MFI.setObjectOffset(FI, -Offset); 870 } 871 872 return Offset; 873 } 874 875 static bool hasRVVSpillWithFIs(MachineFunction &MF, const RISCVInstrInfo &TII) { 876 if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions()) 877 return false; 878 return any_of(MF, [&TII](const MachineBasicBlock &MBB) { 879 return any_of(MBB, [&TII](const MachineInstr &MI) { 880 return TII.isRVVSpill(MI, /*CheckFIs*/ true); 881 }); 882 }); 883 } 884 885 void RISCVFrameLowering::processFunctionBeforeFrameFinalized( 886 MachineFunction &MF, RegScavenger *RS) const { 887 const RISCVRegisterInfo *RegInfo = 888 MF.getSubtarget<RISCVSubtarget>().getRegisterInfo(); 889 MachineFrameInfo &MFI = MF.getFrameInfo(); 890 const TargetRegisterClass *RC = &RISCV::GPRRegClass; 891 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 892 893 int64_t RVVStackSize = assignRVVStackObjectOffsets(MFI); 894 RVFI->setRVVStackSize(RVVStackSize); 895 const RISCVInstrInfo &TII = *MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); 896 897 // estimateStackSize has been observed to under-estimate the final stack 898 // size, so give ourselves wiggle-room by checking for stack size 899 // representable an 11-bit signed field rather than 12-bits. 900 // FIXME: It may be possible to craft a function with a small stack that 901 // still needs an emergency spill slot for branch relaxation. This case 902 // would currently be missed. 903 // RVV loads & stores have no capacity to hold the immediate address offsets 904 // so we must always reserve an emergency spill slot if the MachineFunction 905 // contains any RVV spills. 906 if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF, TII)) { 907 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), 908 RegInfo->getSpillAlign(*RC), false); 909 RS->addScavengingFrameIndex(RegScavFI); 910 // For RVV, scalable stack offsets require up to two scratch registers to 911 // compute the final offset. Reserve an additional emergency spill slot. 912 if (RVVStackSize != 0) { 913 int RVVRegScavFI = MFI.CreateStackObject( 914 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false); 915 RS->addScavengingFrameIndex(RVVRegScavFI); 916 } 917 } 918 919 if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) { 920 RVFI->setCalleeSavedStackSize(0); 921 return; 922 } 923 924 unsigned Size = 0; 925 for (const auto &Info : MFI.getCalleeSavedInfo()) { 926 int FrameIdx = Info.getFrameIdx(); 927 if (MFI.getStackID(FrameIdx) != TargetStackID::Default) 928 continue; 929 930 Size += MFI.getObjectSize(FrameIdx); 931 } 932 RVFI->setCalleeSavedStackSize(Size); 933 934 // Padding required to keep the RVV stack aligned to 8 bytes 935 // within the main stack. We only need this when not using FP. 936 if (RVVStackSize && !hasFP(MF) && Size % 8 != 0) { 937 // Because we add the padding to the size of the stack, adding 938 // getStackAlign() will keep it aligned. 939 RVFI->setRVVPadding(getStackAlign().value()); 940 } 941 } 942 943 static bool hasRVVFrameObject(const MachineFunction &MF) { 944 // Originally, the function will scan all the stack objects to check whether 945 // if there is any scalable vector object on the stack or not. However, it 946 // causes errors in the register allocator. In issue 53016, it returns false 947 // before RA because there is no RVV stack objects. After RA, it returns true 948 // because there are spilling slots for RVV values during RA. It will not 949 // reserve BP during register allocation and generate BP access in the PEI 950 // pass due to the inconsistent behavior of the function. 951 // 952 // The function is changed to use hasVInstructions() as the return value. It 953 // is not precise, but it can make the register allocation correct. 954 // 955 // FIXME: Find a better way to make the decision or revisit the solution in 956 // D103622. 957 // 958 // Refer to https://github.com/llvm/llvm-project/issues/53016. 959 return MF.getSubtarget<RISCVSubtarget>().hasVInstructions(); 960 } 961 962 // Not preserve stack space within prologue for outgoing variables when the 963 // function contains variable size objects or there are vector objects accessed 964 // by the frame pointer. 965 // Let eliminateCallFramePseudoInstr preserve stack space for it. 966 bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 967 return !MF.getFrameInfo().hasVarSizedObjects() && 968 !(hasFP(MF) && hasRVVFrameObject(MF)); 969 } 970 971 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions. 972 MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr( 973 MachineFunction &MF, MachineBasicBlock &MBB, 974 MachineBasicBlock::iterator MI) const { 975 Register SPReg = RISCV::X2; 976 DebugLoc DL = MI->getDebugLoc(); 977 978 if (!hasReservedCallFrame(MF)) { 979 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and 980 // ADJCALLSTACKUP must be converted to instructions manipulating the stack 981 // pointer. This is necessary when there is a variable length stack 982 // allocation (e.g. alloca), which means it's not possible to allocate 983 // space for outgoing arguments from within the function prologue. 984 int64_t Amount = MI->getOperand(0).getImm(); 985 986 if (Amount != 0) { 987 // Ensure the stack remains aligned after adjustment. 988 Amount = alignSPAdjust(Amount); 989 990 if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN) 991 Amount = -Amount; 992 993 adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags); 994 } 995 } 996 997 return MBB.erase(MI); 998 } 999 1000 // We would like to split the SP adjustment to reduce prologue/epilogue 1001 // as following instructions. In this way, the offset of the callee saved 1002 // register could fit in a single store. 1003 // add sp,sp,-2032 1004 // sw ra,2028(sp) 1005 // sw s0,2024(sp) 1006 // sw s1,2020(sp) 1007 // sw s3,2012(sp) 1008 // sw s4,2008(sp) 1009 // add sp,sp,-64 1010 uint64_t 1011 RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const { 1012 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 1013 const MachineFrameInfo &MFI = MF.getFrameInfo(); 1014 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); 1015 uint64_t StackSize = MFI.getStackSize(); 1016 1017 // Disable SplitSPAdjust if save-restore libcall used. The callee saved 1018 // registers will be pushed by the save-restore libcalls, so we don't have to 1019 // split the SP adjustment in this case. 1020 if (RVFI->getLibCallStackSize()) 1021 return 0; 1022 1023 // Return the FirstSPAdjustAmount if the StackSize can not fit in signed 1024 // 12-bit and there exists a callee saved register need to be pushed. 1025 if (!isInt<12>(StackSize) && (CSI.size() > 0)) { 1026 // FirstSPAdjustAmount is choosed as (2048 - StackAlign) 1027 // because 2048 will cause sp = sp + 2048 in epilogue split into 1028 // multi-instructions. The offset smaller than 2048 can fit in signle 1029 // load/store instruction and we have to stick with the stack alignment. 1030 // 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16, 1031 // for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment. 1032 return 2048 - getStackAlign().value(); 1033 } 1034 return 0; 1035 } 1036 1037 bool RISCVFrameLowering::spillCalleeSavedRegisters( 1038 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1039 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { 1040 if (CSI.empty()) 1041 return true; 1042 1043 MachineFunction *MF = MBB.getParent(); 1044 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); 1045 DebugLoc DL; 1046 if (MI != MBB.end() && !MI->isDebugInstr()) 1047 DL = MI->getDebugLoc(); 1048 1049 const char *SpillLibCall = getSpillLibCallName(*MF, CSI); 1050 if (SpillLibCall) { 1051 // Add spill libcall via non-callee-saved register t0. 1052 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) 1053 .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) 1054 .setMIFlag(MachineInstr::FrameSetup); 1055 1056 // Add registers spilled in libcall as liveins. 1057 for (auto &CS : CSI) 1058 MBB.addLiveIn(CS.getReg()); 1059 } 1060 1061 // Manually spill values not spilled by libcall. 1062 const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); 1063 for (auto &CS : NonLibcallCSI) { 1064 // Insert the spill to the stack frame. 1065 Register Reg = CS.getReg(); 1066 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1067 TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), 1068 RC, TRI); 1069 } 1070 1071 return true; 1072 } 1073 1074 bool RISCVFrameLowering::restoreCalleeSavedRegisters( 1075 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1076 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { 1077 if (CSI.empty()) 1078 return true; 1079 1080 MachineFunction *MF = MBB.getParent(); 1081 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); 1082 DebugLoc DL; 1083 if (MI != MBB.end() && !MI->isDebugInstr()) 1084 DL = MI->getDebugLoc(); 1085 1086 // Manually restore values not restored by libcall. 1087 // Keep the same order as in the prologue. There is no need to reverse the 1088 // order in the epilogue. In addition, the return address will be restored 1089 // first in the epilogue. It increases the opportunity to avoid the 1090 // load-to-use data hazard between loading RA and return by RA. 1091 // loadRegFromStackSlot can insert multiple instructions. 1092 const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); 1093 for (auto &CS : NonLibcallCSI) { 1094 Register Reg = CS.getReg(); 1095 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1096 TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI); 1097 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); 1098 } 1099 1100 const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); 1101 if (RestoreLibCall) { 1102 // Add restore libcall via tail call. 1103 MachineBasicBlock::iterator NewMI = 1104 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) 1105 .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) 1106 .setMIFlag(MachineInstr::FrameDestroy); 1107 1108 // Remove trailing returns, since the terminator is now a tail call to the 1109 // restore function. 1110 if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { 1111 NewMI->copyImplicitOps(*MF, *MI); 1112 MI->eraseFromParent(); 1113 } 1114 } 1115 1116 return true; 1117 } 1118 1119 bool RISCVFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1120 // Keep the conventional code flow when not optimizing. 1121 if (MF.getFunction().hasOptNone()) 1122 return false; 1123 1124 return true; 1125 } 1126 1127 bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 1128 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 1129 const MachineFunction *MF = MBB.getParent(); 1130 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>(); 1131 1132 if (!RVFI->useSaveRestoreLibCalls(*MF)) 1133 return true; 1134 1135 // Inserting a call to a __riscv_save libcall requires the use of the register 1136 // t0 (X5) to hold the return address. Therefore if this register is already 1137 // used we can't insert the call. 1138 1139 RegScavenger RS; 1140 RS.enterBasicBlock(*TmpMBB); 1141 return !RS.isRegUsed(RISCV::X5); 1142 } 1143 1144 bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 1145 const MachineFunction *MF = MBB.getParent(); 1146 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 1147 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>(); 1148 1149 if (!RVFI->useSaveRestoreLibCalls(*MF)) 1150 return true; 1151 1152 // Using the __riscv_restore libcalls to restore CSRs requires a tail call. 1153 // This means if we still need to continue executing code within this function 1154 // the restore cannot take place in this basic block. 1155 1156 if (MBB.succ_size() > 1) 1157 return false; 1158 1159 MachineBasicBlock *SuccMBB = 1160 MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin(); 1161 1162 // Doing a tail call should be safe if there are no successors, because either 1163 // we have a returning block or the end of the block is unreachable, so the 1164 // restore will be eliminated regardless. 1165 if (!SuccMBB) 1166 return true; 1167 1168 // The successor can only contain a return, since we would effectively be 1169 // replacing the successor with our own tail return at the end of our block. 1170 return SuccMBB->isReturnBlock() && SuccMBB->size() == 1; 1171 } 1172 1173 bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const { 1174 switch (ID) { 1175 case TargetStackID::Default: 1176 case TargetStackID::ScalableVector: 1177 return true; 1178 case TargetStackID::NoAlloc: 1179 case TargetStackID::SGPRSpill: 1180 case TargetStackID::WasmLocal: 1181 return false; 1182 } 1183 llvm_unreachable("Invalid TargetStackID::Value"); 1184 } 1185 1186 TargetStackID::Value RISCVFrameLowering::getStackIDForScalableVectors() const { 1187 return TargetStackID::ScalableVector; 1188 } 1189