1 //===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands pseudo instructions into target 10 // instructions. This pass should be run after register allocation but before 11 // the post-regalloc scheduling pass. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "RISCV.h" 16 #include "RISCVInstrInfo.h" 17 #include "RISCVTargetMachine.h" 18 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/MC/MCContext.h" 23 24 using namespace llvm; 25 26 #define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass" 27 #define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass" 28 29 namespace { 30 31 class RISCVExpandPseudo : public MachineFunctionPass { 32 public: 33 const RISCVSubtarget *STI; 34 const RISCVInstrInfo *TII; 35 static char ID; 36 37 RISCVExpandPseudo() : MachineFunctionPass(ID) {} 38 39 bool runOnMachineFunction(MachineFunction &MF) override; 40 41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; } 42 43 private: 44 bool expandMBB(MachineBasicBlock &MBB); 45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 46 MachineBasicBlock::iterator &NextMBBI); 47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 48 MachineBasicBlock::iterator &NextMBBI); 49 bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); 50 bool expandVMSET_VMCLR(MachineBasicBlock &MBB, 51 MachineBasicBlock::iterator MBBI, unsigned Opcode); 52 bool expandRV32ZdinxStore(MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator MBBI); 54 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB, 55 MachineBasicBlock::iterator MBBI); 56 #ifndef NDEBUG 57 unsigned getInstSizeInBytes(const MachineFunction &MF) const { 58 unsigned Size = 0; 59 for (auto &MBB : MF) 60 for (auto &MI : MBB) 61 Size += TII->getInstSizeInBytes(MI); 62 return Size; 63 } 64 #endif 65 }; 66 67 char RISCVExpandPseudo::ID = 0; 68 69 bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 70 STI = &MF.getSubtarget<RISCVSubtarget>(); 71 TII = STI->getInstrInfo(); 72 73 #ifndef NDEBUG 74 const unsigned OldSize = getInstSizeInBytes(MF); 75 #endif 76 77 bool Modified = false; 78 for (auto &MBB : MF) 79 Modified |= expandMBB(MBB); 80 81 #ifndef NDEBUG 82 const unsigned NewSize = getInstSizeInBytes(MF); 83 assert(OldSize >= NewSize); 84 #endif 85 return Modified; 86 } 87 88 bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) { 89 bool Modified = false; 90 91 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 92 while (MBBI != E) { 93 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 94 Modified |= expandMI(MBB, MBBI, NMBBI); 95 MBBI = NMBBI; 96 } 97 98 return Modified; 99 } 100 101 bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MBBI, 103 MachineBasicBlock::iterator &NextMBBI) { 104 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the 105 // expanded instructions for each pseudo is correct in the Size field of the 106 // tablegen definition for the pseudo. 107 switch (MBBI->getOpcode()) { 108 case RISCV::PseudoRV32ZdinxSD: 109 return expandRV32ZdinxStore(MBB, MBBI); 110 case RISCV::PseudoRV32ZdinxLD: 111 return expandRV32ZdinxLoad(MBB, MBBI); 112 case RISCV::PseudoCCMOVGPRNoX0: 113 case RISCV::PseudoCCMOVGPR: 114 case RISCV::PseudoCCADD: 115 case RISCV::PseudoCCSUB: 116 case RISCV::PseudoCCAND: 117 case RISCV::PseudoCCOR: 118 case RISCV::PseudoCCXOR: 119 case RISCV::PseudoCCADDW: 120 case RISCV::PseudoCCSUBW: 121 case RISCV::PseudoCCSLL: 122 case RISCV::PseudoCCSRL: 123 case RISCV::PseudoCCSRA: 124 case RISCV::PseudoCCADDI: 125 case RISCV::PseudoCCSLLI: 126 case RISCV::PseudoCCSRLI: 127 case RISCV::PseudoCCSRAI: 128 case RISCV::PseudoCCANDI: 129 case RISCV::PseudoCCORI: 130 case RISCV::PseudoCCXORI: 131 case RISCV::PseudoCCSLLW: 132 case RISCV::PseudoCCSRLW: 133 case RISCV::PseudoCCSRAW: 134 case RISCV::PseudoCCADDIW: 135 case RISCV::PseudoCCSLLIW: 136 case RISCV::PseudoCCSRLIW: 137 case RISCV::PseudoCCSRAIW: 138 case RISCV::PseudoCCANDN: 139 case RISCV::PseudoCCORN: 140 case RISCV::PseudoCCXNOR: 141 return expandCCOp(MBB, MBBI, NextMBBI); 142 case RISCV::PseudoVSETVLI: 143 case RISCV::PseudoVSETVLIX0: 144 case RISCV::PseudoVSETIVLI: 145 return expandVSetVL(MBB, MBBI); 146 case RISCV::PseudoVMCLR_M_B1: 147 case RISCV::PseudoVMCLR_M_B2: 148 case RISCV::PseudoVMCLR_M_B4: 149 case RISCV::PseudoVMCLR_M_B8: 150 case RISCV::PseudoVMCLR_M_B16: 151 case RISCV::PseudoVMCLR_M_B32: 152 case RISCV::PseudoVMCLR_M_B64: 153 // vmclr.m vd => vmxor.mm vd, vd, vd 154 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM); 155 case RISCV::PseudoVMSET_M_B1: 156 case RISCV::PseudoVMSET_M_B2: 157 case RISCV::PseudoVMSET_M_B4: 158 case RISCV::PseudoVMSET_M_B8: 159 case RISCV::PseudoVMSET_M_B16: 160 case RISCV::PseudoVMSET_M_B32: 161 case RISCV::PseudoVMSET_M_B64: 162 // vmset.m vd => vmxnor.mm vd, vd, vd 163 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM); 164 } 165 166 return false; 167 } 168 169 bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MBBI, 171 MachineBasicBlock::iterator &NextMBBI) { 172 173 MachineFunction *MF = MBB.getParent(); 174 MachineInstr &MI = *MBBI; 175 DebugLoc DL = MI.getDebugLoc(); 176 177 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 178 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 179 180 MF->insert(++MBB.getIterator(), TrueBB); 181 MF->insert(++TrueBB->getIterator(), MergeBB); 182 183 // We want to copy the "true" value when the condition is true which means 184 // we need to invert the branch condition to jump over TrueBB when the 185 // condition is false. 186 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm()); 187 CC = RISCVCC::getOppositeBranchCondition(CC); 188 189 // Insert branch instruction. 190 BuildMI(MBB, MBBI, DL, TII->getBrCond(CC)) 191 .addReg(MI.getOperand(1).getReg()) 192 .addReg(MI.getOperand(2).getReg()) 193 .addMBB(MergeBB); 194 195 Register DestReg = MI.getOperand(0).getReg(); 196 assert(MI.getOperand(4).getReg() == DestReg); 197 198 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR || 199 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) { 200 // Add MV. 201 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg) 202 .add(MI.getOperand(5)) 203 .addImm(0); 204 } else { 205 unsigned NewOpc; 206 switch (MI.getOpcode()) { 207 default: 208 llvm_unreachable("Unexpected opcode!"); 209 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break; 210 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break; 211 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break; 212 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break; 213 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break; 214 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break; 215 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break; 216 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break; 217 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; 218 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break; 219 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break; 220 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break; 221 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break; 222 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break; 223 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break; 224 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break; 225 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break; 226 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break; 227 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break; 228 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break; 229 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break; 230 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break; 231 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break; 232 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break; 233 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break; 234 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break; 235 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break; 236 } 237 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg) 238 .add(MI.getOperand(5)) 239 .add(MI.getOperand(6)); 240 } 241 242 TrueBB->addSuccessor(MergeBB); 243 244 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end()); 245 MergeBB->transferSuccessors(&MBB); 246 247 MBB.addSuccessor(TrueBB); 248 MBB.addSuccessor(MergeBB); 249 250 NextMBBI = MBB.end(); 251 MI.eraseFromParent(); 252 253 // Make sure live-ins are correctly attached to this new basic block. 254 LivePhysRegs LiveRegs; 255 computeAndAddLiveIns(LiveRegs, *TrueBB); 256 computeAndAddLiveIns(LiveRegs, *MergeBB); 257 258 return true; 259 } 260 261 bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB, 262 MachineBasicBlock::iterator MBBI) { 263 assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 && 264 "Unexpected instruction format"); 265 266 DebugLoc DL = MBBI->getDebugLoc(); 267 268 assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI || 269 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 || 270 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) && 271 "Unexpected pseudo instruction"); 272 unsigned Opcode; 273 if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI) 274 Opcode = RISCV::VSETIVLI; 275 else 276 Opcode = RISCV::VSETVLI; 277 const MCInstrDesc &Desc = TII->get(Opcode); 278 assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); 279 280 Register DstReg = MBBI->getOperand(0).getReg(); 281 bool DstIsDead = MBBI->getOperand(0).isDead(); 282 BuildMI(MBB, MBBI, DL, Desc) 283 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 284 .add(MBBI->getOperand(1)) // VL 285 .add(MBBI->getOperand(2)); // VType 286 287 MBBI->eraseFromParent(); // The pseudo instruction is gone now. 288 return true; 289 } 290 291 bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB, 292 MachineBasicBlock::iterator MBBI, 293 unsigned Opcode) { 294 DebugLoc DL = MBBI->getDebugLoc(); 295 Register DstReg = MBBI->getOperand(0).getReg(); 296 const MCInstrDesc &Desc = TII->get(Opcode); 297 BuildMI(MBB, MBBI, DL, Desc, DstReg) 298 .addReg(DstReg, RegState::Undef) 299 .addReg(DstReg, RegState::Undef); 300 MBBI->eraseFromParent(); // The pseudo instruction is gone now. 301 return true; 302 } 303 304 // This function expands the PseudoRV32ZdinxSD for storing a double-precision 305 // floating-point value into memory by generating an equivalent instruction 306 // sequence for RV32. 307 bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB, 308 MachineBasicBlock::iterator MBBI) { 309 DebugLoc DL = MBBI->getDebugLoc(); 310 const TargetRegisterInfo *TRI = STI->getRegisterInfo(); 311 Register Lo = 312 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even); 313 Register Hi = 314 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd); 315 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW)) 316 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill())) 317 .addReg(MBBI->getOperand(1).getReg()) 318 .add(MBBI->getOperand(2)); 319 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) { 320 // FIXME: Zdinx RV32 can not work on unaligned memory. 321 assert(!STI->hasFastUnalignedAccess()); 322 323 assert(MBBI->getOperand(2).getOffset() % 8 == 0); 324 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4); 325 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW)) 326 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) 327 .add(MBBI->getOperand(1)) 328 .add(MBBI->getOperand(2)); 329 } else { 330 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4)); 331 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW)) 332 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) 333 .add(MBBI->getOperand(1)) 334 .addImm(MBBI->getOperand(2).getImm() + 4); 335 } 336 MBBI->eraseFromParent(); 337 return true; 338 } 339 340 // This function expands PseudoRV32ZdinxLoad for loading a double-precision 341 // floating-point value from memory into an equivalent instruction sequence for 342 // RV32. 343 bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB, 344 MachineBasicBlock::iterator MBBI) { 345 DebugLoc DL = MBBI->getDebugLoc(); 346 const TargetRegisterInfo *TRI = STI->getRegisterInfo(); 347 Register Lo = 348 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even); 349 Register Hi = 350 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd); 351 352 // If the register of operand 1 is equal to the Lo register, then swap the 353 // order of loading the Lo and Hi statements. 354 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg(); 355 // Order: Lo, Hi 356 if (!IsOp1EqualToLo) { 357 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo) 358 .addReg(MBBI->getOperand(1).getReg()) 359 .add(MBBI->getOperand(2)); 360 } 361 362 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) { 363 auto Offset = MBBI->getOperand(2).getOffset(); 364 assert(MBBI->getOperand(2).getOffset() % 8 == 0); 365 MBBI->getOperand(2).setOffset(Offset + 4); 366 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi) 367 .addReg(MBBI->getOperand(1).getReg()) 368 .add(MBBI->getOperand(2)); 369 MBBI->getOperand(2).setOffset(Offset); 370 } else { 371 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4)); 372 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi) 373 .addReg(MBBI->getOperand(1).getReg()) 374 .addImm(MBBI->getOperand(2).getImm() + 4); 375 } 376 377 // Order: Hi, Lo 378 if (IsOp1EqualToLo) { 379 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo) 380 .addReg(MBBI->getOperand(1).getReg()) 381 .add(MBBI->getOperand(2)); 382 } 383 384 MBBI->eraseFromParent(); 385 return true; 386 } 387 388 class RISCVPreRAExpandPseudo : public MachineFunctionPass { 389 public: 390 const RISCVSubtarget *STI; 391 const RISCVInstrInfo *TII; 392 static char ID; 393 394 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {} 395 396 bool runOnMachineFunction(MachineFunction &MF) override; 397 398 void getAnalysisUsage(AnalysisUsage &AU) const override { 399 AU.setPreservesCFG(); 400 MachineFunctionPass::getAnalysisUsage(AU); 401 } 402 StringRef getPassName() const override { 403 return RISCV_PRERA_EXPAND_PSEUDO_NAME; 404 } 405 406 private: 407 bool expandMBB(MachineBasicBlock &MBB); 408 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 409 MachineBasicBlock::iterator &NextMBBI); 410 bool expandAuipcInstPair(MachineBasicBlock &MBB, 411 MachineBasicBlock::iterator MBBI, 412 MachineBasicBlock::iterator &NextMBBI, 413 unsigned FlagsHi, unsigned SecondOpcode); 414 bool expandLoadLocalAddress(MachineBasicBlock &MBB, 415 MachineBasicBlock::iterator MBBI, 416 MachineBasicBlock::iterator &NextMBBI); 417 bool expandLoadGlobalAddress(MachineBasicBlock &MBB, 418 MachineBasicBlock::iterator MBBI, 419 MachineBasicBlock::iterator &NextMBBI); 420 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB, 421 MachineBasicBlock::iterator MBBI, 422 MachineBasicBlock::iterator &NextMBBI); 423 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB, 424 MachineBasicBlock::iterator MBBI, 425 MachineBasicBlock::iterator &NextMBBI); 426 #ifndef NDEBUG 427 unsigned getInstSizeInBytes(const MachineFunction &MF) const { 428 unsigned Size = 0; 429 for (auto &MBB : MF) 430 for (auto &MI : MBB) 431 Size += TII->getInstSizeInBytes(MI); 432 return Size; 433 } 434 #endif 435 }; 436 437 char RISCVPreRAExpandPseudo::ID = 0; 438 439 bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 440 STI = &MF.getSubtarget<RISCVSubtarget>(); 441 TII = STI->getInstrInfo(); 442 443 #ifndef NDEBUG 444 const unsigned OldSize = getInstSizeInBytes(MF); 445 #endif 446 447 bool Modified = false; 448 for (auto &MBB : MF) 449 Modified |= expandMBB(MBB); 450 451 #ifndef NDEBUG 452 const unsigned NewSize = getInstSizeInBytes(MF); 453 assert(OldSize >= NewSize); 454 #endif 455 return Modified; 456 } 457 458 bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) { 459 bool Modified = false; 460 461 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 462 while (MBBI != E) { 463 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 464 Modified |= expandMI(MBB, MBBI, NMBBI); 465 MBBI = NMBBI; 466 } 467 468 return Modified; 469 } 470 471 bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB, 472 MachineBasicBlock::iterator MBBI, 473 MachineBasicBlock::iterator &NextMBBI) { 474 475 switch (MBBI->getOpcode()) { 476 case RISCV::PseudoLLA: 477 return expandLoadLocalAddress(MBB, MBBI, NextMBBI); 478 case RISCV::PseudoLGA: 479 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI); 480 case RISCV::PseudoLA_TLS_IE: 481 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI); 482 case RISCV::PseudoLA_TLS_GD: 483 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI); 484 } 485 return false; 486 } 487 488 bool RISCVPreRAExpandPseudo::expandAuipcInstPair( 489 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 490 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi, 491 unsigned SecondOpcode) { 492 MachineFunction *MF = MBB.getParent(); 493 MachineInstr &MI = *MBBI; 494 DebugLoc DL = MI.getDebugLoc(); 495 496 Register DestReg = MI.getOperand(0).getReg(); 497 Register ScratchReg = 498 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); 499 500 MachineOperand &Symbol = MI.getOperand(1); 501 Symbol.setTargetFlags(FlagsHi); 502 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi"); 503 504 MachineInstr *MIAUIPC = 505 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol); 506 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol); 507 508 MachineInstr *SecondMI = 509 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) 510 .addReg(ScratchReg) 511 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO); 512 513 if (MI.hasOneMemOperand()) 514 SecondMI->addMemOperand(*MF, *MI.memoperands_begin()); 515 516 MI.eraseFromParent(); 517 return true; 518 } 519 520 bool RISCVPreRAExpandPseudo::expandLoadLocalAddress( 521 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 522 MachineBasicBlock::iterator &NextMBBI) { 523 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI, 524 RISCV::ADDI); 525 } 526 527 bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress( 528 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 529 MachineBasicBlock::iterator &NextMBBI) { 530 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW; 531 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI, 532 SecondOpcode); 533 } 534 535 bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress( 536 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 537 MachineBasicBlock::iterator &NextMBBI) { 538 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW; 539 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI, 540 SecondOpcode); 541 } 542 543 bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress( 544 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 545 MachineBasicBlock::iterator &NextMBBI) { 546 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI, 547 RISCV::ADDI); 548 } 549 550 } // end of anonymous namespace 551 552 INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo", 553 RISCV_EXPAND_PSEUDO_NAME, false, false) 554 555 INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo", 556 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false) 557 558 namespace llvm { 559 560 FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); } 561 FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); } 562 563 } // end of namespace llvm 564