1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<(all_of FeatureStdExtM), 20 "'M' (Integer Multiplication and Division)">; 21 22def FeatureStdExtA 23 : SubtargetFeature<"a", "HasStdExtA", "true", 24 "'A' (Atomic Instructions)">; 25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26 AssemblerPredicate<(all_of FeatureStdExtA), 27 "'A' (Atomic Instructions)">; 28 29def FeatureStdExtF 30 : SubtargetFeature<"f", "HasStdExtF", "true", 31 "'F' (Single-Precision Floating-Point)">; 32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33 AssemblerPredicate<(all_of FeatureStdExtF), 34 "'F' (Single-Precision Floating-Point)">; 35 36def FeatureStdExtD 37 : SubtargetFeature<"d", "HasStdExtD", "true", 38 "'D' (Double-Precision Floating-Point)", 39 [FeatureStdExtF]>; 40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41 AssemblerPredicate<(all_of FeatureStdExtD), 42 "'D' (Double-Precision Floating-Point)">; 43 44def FeatureStdExtZfhmin 45 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", 46 "'Zfhmin' (Half-Precision Floating-Point Minimal)", 47 [FeatureStdExtF]>; 48def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, 49 AssemblerPredicate<(all_of FeatureStdExtZfhmin), 50 "'Zfhmin' (Half-Precision Floating-Point Minimal)">; 51 52def FeatureStdExtZfh 53 : SubtargetFeature<"zfh", "HasStdExtZfh", "true", 54 "'Zfh' (Half-Precision Floating-Point)", 55 [FeatureStdExtF]>; 56def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 57 AssemblerPredicate<(all_of FeatureStdExtZfh), 58 "'Zfh' (Half-Precision Floating-Point)">; 59 60def HasStdExtZfhOrZfhmin 61 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">, 62 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin), 63 "'Zfh' (Half-Precision Floating-Point) or " 64 "'Zfhmin' (Half-Precision Floating-Point Minimal)">; 65 66def FeatureStdExtC 67 : SubtargetFeature<"c", "HasStdExtC", "true", 68 "'C' (Compressed Instructions)">; 69def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 70 AssemblerPredicate<(all_of FeatureStdExtC), 71 "'C' (Compressed Instructions)">; 72 73def FeatureStdExtZba 74 : SubtargetFeature<"zba", "HasStdExtZba", "true", 75 "'Zba' (Address Generation Instructions)">; 76def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, 77 AssemblerPredicate<(all_of FeatureStdExtZba), 78 "'Zba' (Address Generation Instructions)">; 79def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; 80 81def FeatureStdExtZbb 82 : SubtargetFeature<"zbb", "HasStdExtZbb", "true", 83 "'Zbb' (Basic Bit-Manipulation)">; 84def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 85 AssemblerPredicate<(all_of FeatureStdExtZbb), 86 "'Zbb' (Basic Bit-Manipulation)">; 87 88def FeatureStdExtZbc 89 : SubtargetFeature<"zbc", "HasStdExtZbc", "true", 90 "'Zbc' (Carry-Less Multiplication)">; 91def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 92 AssemblerPredicate<(all_of FeatureStdExtZbc), 93 "'Zbc' (Carry-Less Multiplication)">; 94 95def FeatureStdExtZbe 96 : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", 97 "'Zbe' (Extract-Deposit 'Zb' Instructions)">; 98def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, 99 AssemblerPredicate<(all_of FeatureStdExtZbe), 100 "'Zbe' (Extract-Deposit 'Zb' Instructions)">; 101 102def FeatureStdExtZbf 103 : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", 104 "'Zbf' (Bit-Field 'Zb' Instructions)">; 105def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, 106 AssemblerPredicate<(all_of FeatureStdExtZbf), 107 "'Zbf' (Bit-Field 'Zb' Instructions)">; 108 109def FeatureStdExtZbm 110 : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", 111 "'Zbm' (Matrix 'Zb' Instructions)">; 112def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, 113 AssemblerPredicate<(all_of FeatureStdExtZbm), 114 "'Zbm' (Matrix 'Zb' Instructions)">; 115 116def FeatureStdExtZbp 117 : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", 118 "'Zbp' (Permutation 'Zb' Instructions)">; 119def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, 120 AssemblerPredicate<(all_of FeatureStdExtZbp), 121 "'Zbp' (Permutation 'Zb' Instructions)">; 122 123def FeatureStdExtZbr 124 : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", 125 "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; 126def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, 127 AssemblerPredicate<(all_of FeatureStdExtZbr), 128 "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; 129 130def FeatureStdExtZbs 131 : SubtargetFeature<"zbs", "HasStdExtZbs", "true", 132 "'Zbs' (Single-Bit Instructions)">; 133def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 134 AssemblerPredicate<(all_of FeatureStdExtZbs), 135 "'Zbs' (Single-Bit Instructions)">; 136 137def FeatureStdExtZbt 138 : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", 139 "'Zbt' (Ternary 'Zb' Instructions)">; 140def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, 141 AssemblerPredicate<(all_of FeatureStdExtZbt), 142 "'Zbt' (Ternary 'Zb' Instructions)">; 143 144// Some instructions belong to both the basic and the permutation 145// subextensions. They should be enabled if either has been specified. 146def HasStdExtZbbOrZbp 147 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, 148 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp), 149 "'Zbb' (Basic Bit-Manipulation) or " 150 "'Zbp' (Permutation 'Zb' Instructions)">; 151 152def FeatureStdExtZbkb 153 : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", 154 "'Zbkb' (Bitmanip instructions for Cryptography)">; 155def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, 156 AssemblerPredicate<(all_of FeatureStdExtZbkb), 157 "'Zbkb' (Bitmanip instructions for Cryptography)">; 158 159def FeatureStdExtZbkx 160 : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true", 161 "'Zbkx' (Crossbar permutation instructions)">; 162def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, 163 AssemblerPredicate<(all_of FeatureStdExtZbkx), 164 "'Zbkx' (Crossbar permutation instructions)">; 165 166def HasStdExtZbpOrZbkx 167 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">, 168 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkx), 169 "'Zbp' (Permutation 'Zb' Instructions) or " 170 "'Zbkx' (Crossbar permutation instructions)">; 171 172def HasStdExtZbpOrZbkb 173 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, 174 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb), 175 "'Zbp' (Permutation 'Zb' Instructions) or " 176 "'Zbkb' (Bitmanip instructions for Cryptography)">; 177 178def HasStdExtZbbOrZbkb 179 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">, 180 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), 181 "'Zbb' (Basic Bit-Manipulation) or " 182 "'Zbkb' (Bitmanip instructions for Cryptography)">; 183 184def HasStdExtZbbOrZbpOrZbkb 185 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, 186 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb), 187 "'Zbb' (Basic Bit-Manipulation) or " 188 "'Zbp' (Permutation 'Zb' Instructions) or " 189 "'Zbkb' (Bitmanip instructions for Cryptography)">; 190 191// The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled. 192def FeatureStdExtZbkc 193 : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true", 194 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 195def HasStdExtZbkc 196 : Predicate<"Subtarget->hasStdExtZbkc()">, 197 AssemblerPredicate<(all_of FeatureStdExtZbkc), 198 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 199 200def HasStdExtZbcOrZbkc 201 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, 202 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), 203 "'Zbc' (Carry-Less Multiplication) or " 204 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 205 206def FeatureStdExtZknd 207 : SubtargetFeature<"zknd", "HasStdExtZknd", "true", 208 "'Zknd' (NIST Suite: AES Decryption)">; 209def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, 210 AssemblerPredicate<(all_of FeatureStdExtZknd), 211 "'Zknd' (NIST Suite: AES Decryption)">; 212 213def FeatureStdExtZkne 214 : SubtargetFeature<"zkne", "HasStdExtZkne", "true", 215 "'Zkne' (NIST Suite: AES Encryption)">; 216def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, 217 AssemblerPredicate<(all_of FeatureStdExtZkne), 218 "'Zkne' (NIST Suite: AES Encryption)">; 219 220// Some instructions belong to both Zknd and Zkne subextensions. 221// They should be enabled if either has been specified. 222def HasStdExtZkndOrZkne 223 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, 224 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), 225 "'Zknd' (NIST Suite: AES Decryption) or " 226 "'Zkne' (NIST Suite: AES Encryption)">; 227 228def FeatureStdExtZknh 229 : SubtargetFeature<"zknh", "HasStdExtZknh", "true", 230 "'Zknh' (NIST Suite: Hash Function Instructions)">; 231def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, 232 AssemblerPredicate<(all_of FeatureStdExtZknh), 233 "'Zknh' (NIST Suite: Hash Function Instructions)">; 234 235def FeatureStdExtZksed 236 : SubtargetFeature<"zksed", "HasStdExtZksed", "true", 237 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 238def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, 239 AssemblerPredicate<(all_of FeatureStdExtZksed), 240 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 241 242def FeatureStdExtZksh 243 : SubtargetFeature<"zksh", "HasStdExtZksh", "true", 244 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 245def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, 246 AssemblerPredicate<(all_of FeatureStdExtZksh), 247 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 248 249def FeatureStdExtZkr 250 : SubtargetFeature<"zkr", "HasStdExtZkr", "true", 251 "'Zkr' (Entropy Source Extension)">; 252def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, 253 AssemblerPredicate<(all_of FeatureStdExtZkr), 254 "'Zkr' (Entropy Source Extension)">; 255 256def FeatureStdExtZkn 257 : SubtargetFeature<"zkn", "HasStdExtZkn", "true", 258 "'Zkn' (NIST Algorithm Suite)", 259 [FeatureStdExtZbkb, 260 FeatureStdExtZbkc, 261 FeatureStdExtZbkx, 262 FeatureStdExtZkne, 263 FeatureStdExtZknd, 264 FeatureStdExtZknh]>; 265 266def FeatureStdExtZks 267 : SubtargetFeature<"zks", "HasStdExtZks", "true", 268 "'Zks' (ShangMi Algorithm Suite)", 269 [FeatureStdExtZbkb, 270 FeatureStdExtZbkc, 271 FeatureStdExtZbkx, 272 FeatureStdExtZksed, 273 FeatureStdExtZksh]>; 274 275def FeatureStdExtZkt 276 : SubtargetFeature<"zkt", "HasStdExtZkt", "true", 277 "'Zkt' (Data Independent Execution Latency)">; 278 279def FeatureStdExtZk 280 : SubtargetFeature<"zk", "HasStdExtZk", "true", 281 "'Zk' (Standard scalar cryptography extension)", 282 [FeatureStdExtZkn, 283 FeatureStdExtZkr, 284 FeatureStdExtZkt]>; 285 286def FeatureNoRVCHints 287 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 288 "Disable RVC Hint Instructions.">; 289def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 290 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 291 "RVC Hint Instructions">; 292 293def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "ExtZvl::Zvl32b", 294 "'Zvl' (Minimum Vector Length) 32">; 295 296foreach i = { 6-15 } in { 297 defvar I = !shl(1, i); 298 def FeatureStdExtZvl#I#b : 299 SubtargetFeature<"zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b", 300 "'Zvl' (Minimum Vector Length) "#I, 301 [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; 302} 303 304def FeatureStdExtZve32x 305 : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true", 306 "'Zve32x' (Vector Extensions for Embedded Processors " 307 "with maximal 32 EEW)", 308 [FeatureStdExtZvl32b]>; 309 310def FeatureStdExtZve32f 311 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true", 312 "'Zve32f' (Vector Extensions for Embedded Processors " 313 "with maximal 32 EEW and F extension)", 314 [FeatureStdExtZve32x]>; 315 316def FeatureStdExtZve64x 317 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true", 318 "'Zve64x' (Vector Extensions for Embedded Processors " 319 "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>; 320 321def FeatureStdExtZve64f 322 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true", 323 "'Zve64f' (Vector Extensions for Embedded Processors " 324 "with maximal 64 EEW and F extension)", 325 [FeatureStdExtZve32f, FeatureStdExtZve64x]>; 326 327def FeatureStdExtZve64d 328 : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true", 329 "'Zve64d' (Vector Extensions for Embedded Processors " 330 "with maximal 64 EEW, F and D extension)", 331 [FeatureStdExtZve64f]>; 332 333def FeatureStdExtV 334 : SubtargetFeature<"v", "HasStdExtV", "true", 335 "'V' (Vector Extension for Application Processors)", 336 [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>; 337 338def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, 339 AssemblerPredicate< 340 (any_of FeatureStdExtZve32x, FeatureStdExtV), 341 "'V' (Vector Extension for Application Processors), 'Zve32x' or " 342 "'Zve64x' (Vector Extensions for Embedded Processors)">; 343def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">, 344 AssemblerPredicate< 345 (any_of FeatureStdExtZve64x, FeatureStdExtV), 346 "'V' (Vector Extension for Application Processors) or 'Zve64x' " 347 "(Vector Extensions for Embedded Processors)">; 348def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, 349 AssemblerPredicate< 350 (any_of FeatureStdExtZve32f, FeatureStdExtV), 351 "'V' (Vector Extension for Application Processors), 'Zve32f', " 352 "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; 353 354def Feature64Bit 355 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 356def IsRV64 : Predicate<"Subtarget->is64Bit()">, 357 AssemblerPredicate<(all_of Feature64Bit), 358 "RV64I Base Instruction Set">; 359def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 360 AssemblerPredicate<(all_of (not Feature64Bit)), 361 "RV32I Base Instruction Set">; 362 363defvar RV32 = DefaultMode; 364def RV64 : HwMode<"+64bit">; 365 366def FeatureRV32E 367 : SubtargetFeature<"e", "IsRV32E", "true", 368 "Implements RV32E (provides 16 rather than 32 GPRs)">; 369def IsRV32E : Predicate<"Subtarget->isRV32E()">, 370 AssemblerPredicate<(all_of FeatureRV32E)>; 371 372def FeatureRelax 373 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 374 "Enable Linker relaxation.">; 375 376foreach i = {1-31} in 377 def FeatureReserveX#i : 378 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 379 "true", "Reserve X"#i>; 380 381def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 382 "true", "Enable save/restore.">; 383 384def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", 385 "SiFive 7-Series processors">; 386 387//===----------------------------------------------------------------------===// 388// Named operands for CSR instructions. 389//===----------------------------------------------------------------------===// 390 391include "RISCVSystemOperands.td" 392 393//===----------------------------------------------------------------------===// 394// Registers, calling conventions, instruction descriptions. 395//===----------------------------------------------------------------------===// 396 397include "RISCVSchedule.td" 398include "RISCVRegisterInfo.td" 399include "RISCVCallingConv.td" 400include "RISCVInstrInfo.td" 401include "RISCVRegisterBanks.td" 402include "RISCVSchedRocket.td" 403include "RISCVSchedSiFive7.td" 404 405//===----------------------------------------------------------------------===// 406// RISC-V processors supported. 407//===----------------------------------------------------------------------===// 408 409def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 410def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 411 412def : ProcessorModel<"rocket-rv32", RocketModel, []>; 413def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; 414 415def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [], 416 [TuneSiFive7]>; 417def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit], 418 [TuneSiFive7]>; 419 420def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM, 421 FeatureStdExtC]>; 422 423def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM, 424 FeatureStdExtA, 425 FeatureStdExtC]>; 426 427def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM, 428 FeatureStdExtA, 429 FeatureStdExtF, 430 FeatureStdExtC]>; 431 432def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, 433 FeatureStdExtA, 434 FeatureStdExtC]>; 435 436def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM, 437 FeatureStdExtA, 438 FeatureStdExtF, 439 FeatureStdExtC]>; 440 441def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, 442 FeatureStdExtA, 443 FeatureStdExtF, 444 FeatureStdExtC], 445 [TuneSiFive7]>; 446 447def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, 448 FeatureStdExtM, 449 FeatureStdExtA, 450 FeatureStdExtC]>; 451 452def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit, 453 FeatureStdExtM, 454 FeatureStdExtA, 455 FeatureStdExtC]>; 456 457def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit, 458 FeatureStdExtM, 459 FeatureStdExtA, 460 FeatureStdExtF, 461 FeatureStdExtD, 462 FeatureStdExtC]>; 463 464def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit, 465 FeatureStdExtM, 466 FeatureStdExtA, 467 FeatureStdExtF, 468 FeatureStdExtD, 469 FeatureStdExtC], 470 [TuneSiFive7]>; 471 472def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, 473 FeatureStdExtM, 474 FeatureStdExtA, 475 FeatureStdExtF, 476 FeatureStdExtD, 477 FeatureStdExtC]>; 478 479def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit, 480 FeatureStdExtM, 481 FeatureStdExtA, 482 FeatureStdExtF, 483 FeatureStdExtD, 484 FeatureStdExtC], 485 [TuneSiFive7]>; 486 487//===----------------------------------------------------------------------===// 488// Define the RISC-V target. 489//===----------------------------------------------------------------------===// 490 491def RISCVInstrInfo : InstrInfo { 492 let guessInstructionProperties = 0; 493} 494 495def RISCVAsmParser : AsmParser { 496 let ShouldEmitMatchRegisterAltName = 1; 497 let AllowDuplicateRegisterNames = 1; 498} 499 500def RISCVAsmWriter : AsmWriter { 501 int PassSubtarget = 1; 502} 503 504def RISCV : Target { 505 let InstructionSet = RISCVInstrInfo; 506 let AssemblyParsers = [RISCVAsmParser]; 507 let AssemblyWriters = [RISCVAsmWriter]; 508 let AllowRegisterRenaming = 1; 509} 510