1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<"FeatureStdExtM">; 20 21def FeatureStdExtA 22 : SubtargetFeature<"a", "HasStdExtA", "true", 23 "'A' (Atomic Instructions)">; 24def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 25 AssemblerPredicate<"FeatureStdExtA">; 26 27def FeatureStdExtF 28 : SubtargetFeature<"f", "HasStdExtF", "true", 29 "'F' (Single-Precision Floating-Point)">; 30def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 31 AssemblerPredicate<"FeatureStdExtF">; 32 33def FeatureStdExtD 34 : SubtargetFeature<"d", "HasStdExtD", "true", 35 "'D' (Double-Precision Floating-Point)", 36 [FeatureStdExtF]>; 37def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 38 AssemblerPredicate<"FeatureStdExtD">; 39 40def FeatureStdExtC 41 : SubtargetFeature<"c", "HasStdExtC", "true", 42 "'C' (Compressed Instructions)">; 43def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 44 AssemblerPredicate<"FeatureStdExtC">; 45 46 47def Feature64Bit 48 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 49def IsRV64 : Predicate<"Subtarget->is64Bit()">, 50 AssemblerPredicate<"Feature64Bit">; 51def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 52 AssemblerPredicate<"!Feature64Bit">; 53 54def RV64 : HwMode<"+64bit">; 55def RV32 : HwMode<"-64bit">; 56 57def FeatureRV32E 58 : SubtargetFeature<"e", "IsRV32E", "true", 59 "Implements RV32E (provides 16 rather than 32 GPRs)">; 60def IsRV32E : Predicate<"Subtarget->isRV32E()">, 61 AssemblerPredicate<"FeatureRV32E">; 62 63def FeatureRelax 64 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 65 "Enable Linker relaxation.">; 66 67//===----------------------------------------------------------------------===// 68// Named operands for CSR instructions. 69//===----------------------------------------------------------------------===// 70 71include "RISCVSystemOperands.td" 72 73//===----------------------------------------------------------------------===// 74// Registers, calling conventions, instruction descriptions. 75//===----------------------------------------------------------------------===// 76 77include "RISCVRegisterInfo.td" 78include "RISCVCallingConv.td" 79include "RISCVInstrInfo.td" 80 81//===----------------------------------------------------------------------===// 82// RISC-V processors supported. 83//===----------------------------------------------------------------------===// 84 85def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 86 87def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 88 89//===----------------------------------------------------------------------===// 90// Define the RISC-V target. 91//===----------------------------------------------------------------------===// 92 93def RISCVInstrInfo : InstrInfo { 94 let guessInstructionProperties = 0; 95} 96 97def RISCVAsmParser : AsmParser { 98 let ShouldEmitMatchRegisterAltName = 1; 99 let AllowDuplicateRegisterNames = 1; 100} 101 102def RISCVAsmWriter : AsmWriter { 103 int PassSubtarget = 1; 104} 105 106def RISCV : Target { 107 let InstructionSet = RISCVInstrInfo; 108 let AssemblyParsers = [RISCVAsmParser]; 109 let AssemblyWriters = [RISCVAsmWriter]; 110 let AllowRegisterRenaming = 1; 111} 112