1*e8d8bef9SDimitry Andric //===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===// 2*e8d8bef9SDimitry Andric // 3*e8d8bef9SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*e8d8bef9SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*e8d8bef9SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*e8d8bef9SDimitry Andric // 7*e8d8bef9SDimitry Andric //===----------------------------------------------------------------------===// 8*e8d8bef9SDimitry Andric 9*e8d8bef9SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_MATINT_H 10*e8d8bef9SDimitry Andric #define LLVM_LIB_TARGET_RISCV_MATINT_H 11*e8d8bef9SDimitry Andric 12*e8d8bef9SDimitry Andric #include "llvm/ADT/SmallVector.h" 13*e8d8bef9SDimitry Andric #include <cstdint> 14*e8d8bef9SDimitry Andric 15*e8d8bef9SDimitry Andric namespace llvm { 16*e8d8bef9SDimitry Andric class APInt; 17*e8d8bef9SDimitry Andric 18*e8d8bef9SDimitry Andric namespace RISCVMatInt { 19*e8d8bef9SDimitry Andric struct Inst { 20*e8d8bef9SDimitry Andric unsigned Opc; 21*e8d8bef9SDimitry Andric int64_t Imm; 22*e8d8bef9SDimitry Andric 23*e8d8bef9SDimitry Andric Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} 24*e8d8bef9SDimitry Andric }; 25*e8d8bef9SDimitry Andric using InstSeq = SmallVector<Inst, 8>; 26*e8d8bef9SDimitry Andric 27*e8d8bef9SDimitry Andric // Helper to generate an instruction sequence that will materialise the given 28*e8d8bef9SDimitry Andric // immediate value into a register. A sequence of instructions represented by 29*e8d8bef9SDimitry Andric // a simple struct produced rather than directly emitting the instructions in 30*e8d8bef9SDimitry Andric // order to allow this helper to be used from both the MC layer and during 31*e8d8bef9SDimitry Andric // instruction selection. 32*e8d8bef9SDimitry Andric void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res); 33*e8d8bef9SDimitry Andric 34*e8d8bef9SDimitry Andric // Helper to estimate the number of instructions required to materialise the 35*e8d8bef9SDimitry Andric // given immediate value into a register. This estimate does not account for 36*e8d8bef9SDimitry Andric // `Val` possibly fitting into an immediate, and so may over-estimate. 37*e8d8bef9SDimitry Andric // 38*e8d8bef9SDimitry Andric // This will attempt to produce instructions to materialise `Val` as an 39*e8d8bef9SDimitry Andric // `Size`-bit immediate. `IsRV64` should match the target architecture. 40*e8d8bef9SDimitry Andric int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64); 41*e8d8bef9SDimitry Andric } // namespace RISCVMatInt 42*e8d8bef9SDimitry Andric } // namespace llvm 43*e8d8bef9SDimitry Andric #endif 44