1e8d8bef9SDimitry Andric //===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===// 2e8d8bef9SDimitry Andric // 3e8d8bef9SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric // 7e8d8bef9SDimitry Andric //===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric 904eeddc0SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H 1004eeddc0SDimitry Andric #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H 11e8d8bef9SDimitry Andric 12e8d8bef9SDimitry Andric #include "llvm/ADT/SmallVector.h" 13fe6060f1SDimitry Andric #include "llvm/MC/SubtargetFeature.h" 14e8d8bef9SDimitry Andric #include <cstdint> 15e8d8bef9SDimitry Andric 16e8d8bef9SDimitry Andric namespace llvm { 17e8d8bef9SDimitry Andric class APInt; 18e8d8bef9SDimitry Andric 19e8d8bef9SDimitry Andric namespace RISCVMatInt { 20*81ad6265SDimitry Andric 21*81ad6265SDimitry Andric enum OpndKind { 22*81ad6265SDimitry Andric RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI 23*81ad6265SDimitry Andric Imm, // LUI 24*81ad6265SDimitry Andric RegReg, // SH1ADD/SH2ADD/SH3ADD 25*81ad6265SDimitry Andric RegX0, // ADD_UW 26*81ad6265SDimitry Andric }; 27*81ad6265SDimitry Andric 28e8d8bef9SDimitry Andric struct Inst { 29e8d8bef9SDimitry Andric unsigned Opc; 30e8d8bef9SDimitry Andric int64_t Imm; 31e8d8bef9SDimitry Andric 32e8d8bef9SDimitry Andric Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} 33*81ad6265SDimitry Andric 34*81ad6265SDimitry Andric OpndKind getOpndKind() const; 35e8d8bef9SDimitry Andric }; 36e8d8bef9SDimitry Andric using InstSeq = SmallVector<Inst, 8>; 37e8d8bef9SDimitry Andric 38e8d8bef9SDimitry Andric // Helper to generate an instruction sequence that will materialise the given 39fe6060f1SDimitry Andric // immediate value into a register. A sequence of instructions represented by a 40fe6060f1SDimitry Andric // simple struct is produced rather than directly emitting the instructions in 41e8d8bef9SDimitry Andric // order to allow this helper to be used from both the MC layer and during 42e8d8bef9SDimitry Andric // instruction selection. 43fe6060f1SDimitry Andric InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures); 44e8d8bef9SDimitry Andric 45e8d8bef9SDimitry Andric // Helper to estimate the number of instructions required to materialise the 46e8d8bef9SDimitry Andric // given immediate value into a register. This estimate does not account for 47e8d8bef9SDimitry Andric // `Val` possibly fitting into an immediate, and so may over-estimate. 48e8d8bef9SDimitry Andric // 49e8d8bef9SDimitry Andric // This will attempt to produce instructions to materialise `Val` as an 50fe6060f1SDimitry Andric // `Size`-bit immediate. 51fe6060f1SDimitry Andric // 52fe6060f1SDimitry Andric // If CompressionCost is true it will use a different cost calculation if RVC is 53fe6060f1SDimitry Andric // enabled. This should be used to compare two different sequences to determine 54fe6060f1SDimitry Andric // which is more compressible. 55fe6060f1SDimitry Andric int getIntMatCost(const APInt &Val, unsigned Size, 56fe6060f1SDimitry Andric const FeatureBitset &ActiveFeatures, 57fe6060f1SDimitry Andric bool CompressionCost = false); 58e8d8bef9SDimitry Andric } // namespace RISCVMatInt 59e8d8bef9SDimitry Andric } // namespace llvm 60e8d8bef9SDimitry Andric #endif 61