1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISCV target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVBaseInfo.h" 15 #include "llvm/ADT/ArrayRef.h" 16 #include "llvm/ADT/Triple.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/Support/RISCVISAInfo.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 namespace llvm { 22 23 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; 24 25 namespace RISCVSysReg { 26 #define GET_SysRegsList_IMPL 27 #include "RISCVGenSearchableTables.inc" 28 } // namespace RISCVSysReg 29 30 namespace RISCVABI { 31 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 32 StringRef ABIName) { 33 auto TargetABI = getTargetABI(ABIName); 34 bool IsRV64 = TT.isArch64Bit(); 35 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; 36 37 if (!ABIName.empty() && TargetABI == ABI_Unknown) { 38 errs() 39 << "'" << ABIName 40 << "' is not a recognized ABI for this target (ignoring target-abi)\n"; 41 } else if (ABIName.startswith("ilp32") && IsRV64) { 42 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " 43 "target-abi)\n"; 44 TargetABI = ABI_Unknown; 45 } else if (ABIName.startswith("lp64") && !IsRV64) { 46 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " 47 "target-abi)\n"; 48 TargetABI = ABI_Unknown; 49 } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { 50 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 51 errs() 52 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; 53 TargetABI = ABI_Unknown; 54 } 55 56 if (TargetABI != ABI_Unknown) 57 return TargetABI; 58 59 // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given 60 // or an invalid/unrecognised string is given. In the future, it might be 61 // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when 62 // hardware support for floating point is present. 63 if (IsRV32E) 64 return ABI_ILP32E; 65 if (IsRV64) 66 return ABI_LP64; 67 return ABI_ILP32; 68 } 69 70 ABI getTargetABI(StringRef ABIName) { 71 auto TargetABI = StringSwitch<ABI>(ABIName) 72 .Case("ilp32", ABI_ILP32) 73 .Case("ilp32f", ABI_ILP32F) 74 .Case("ilp32d", ABI_ILP32D) 75 .Case("ilp32e", ABI_ILP32E) 76 .Case("lp64", ABI_LP64) 77 .Case("lp64f", ABI_LP64F) 78 .Case("lp64d", ABI_LP64D) 79 .Default(ABI_Unknown); 80 return TargetABI; 81 } 82 83 // To avoid the BP value clobbered by a function call, we need to choose a 84 // callee saved register to save the value. RV32E only has X8 and X9 as callee 85 // saved registers and X8 will be used as fp. So we choose X9 as bp. 86 MCRegister getBPReg() { return RISCV::X9; } 87 88 // Returns the register holding shadow call stack pointer. 89 MCRegister getSCSPReg() { return RISCV::X18; } 90 91 } // namespace RISCVABI 92 93 namespace RISCVFeatures { 94 95 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { 96 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) 97 report_fatal_error("RV64 target requires an RV64 CPU"); 98 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) 99 report_fatal_error("RV32 target requires an RV32 CPU"); 100 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) 101 report_fatal_error("RV32E can't be enabled for an RV64 target"); 102 } 103 104 void toFeatureVector(std::vector<std::string> &FeatureVector, 105 const FeatureBitset &FeatureBits) { 106 for (auto Feature : RISCVFeatureKV) { 107 if (FeatureBits[Feature.Value] && 108 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) 109 FeatureVector.push_back(std::string("+") + Feature.Key); 110 } 111 } 112 113 } // namespace RISCVFeatures 114 115 // Encode VTYPE into the binary format used by the the VSETVLI instruction which 116 // is used by our MC layer representation. 117 // 118 // Bits | Name | Description 119 // -----+------------+------------------------------------------------ 120 // 7 | vma | Vector mask agnostic 121 // 6 | vta | Vector tail agnostic 122 // 5:3 | vsew[2:0] | Standard element width (SEW) setting 123 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting 124 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, 125 bool TailAgnostic, bool MaskAgnostic) { 126 assert(isValidSEW(SEW) && "Invalid SEW"); 127 unsigned VLMULBits = static_cast<unsigned>(VLMUL); 128 unsigned VSEWBits = Log2_32(SEW) - 3; 129 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); 130 if (TailAgnostic) 131 VTypeI |= 0x40; 132 if (MaskAgnostic) 133 VTypeI |= 0x80; 134 135 return VTypeI; 136 } 137 138 std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) { 139 switch (VLMUL) { 140 default: 141 llvm_unreachable("Unexpected LMUL value!"); 142 case RISCVII::VLMUL::LMUL_1: 143 case RISCVII::VLMUL::LMUL_2: 144 case RISCVII::VLMUL::LMUL_4: 145 case RISCVII::VLMUL::LMUL_8: 146 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false); 147 case RISCVII::VLMUL::LMUL_F2: 148 case RISCVII::VLMUL::LMUL_F4: 149 case RISCVII::VLMUL::LMUL_F8: 150 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true); 151 } 152 } 153 154 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) { 155 unsigned Sew = getSEW(VType); 156 OS << "e" << Sew; 157 158 unsigned LMul; 159 bool Fractional; 160 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); 161 162 if (Fractional) 163 OS << ", mf"; 164 else 165 OS << ", m"; 166 OS << LMul; 167 168 if (isTailAgnostic(VType)) 169 OS << ", ta"; 170 else 171 OS << ", tu"; 172 173 if (isMaskAgnostic(VType)) 174 OS << ", ma"; 175 else 176 OS << ", mu"; 177 } 178 179 } // namespace llvm 180