1bdd1243dSDimitry Andric //===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===// 2bdd1243dSDimitry Andric // 3bdd1243dSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4bdd1243dSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5bdd1243dSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6bdd1243dSDimitry Andric // 7bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 8bdd1243dSDimitry Andric /// \file 9*06c3fb27SDimitry Andric /// This file implements the targeting of the RegisterBankInfo class for RISC-V. 10bdd1243dSDimitry Andric /// \todo This should be generated by TableGen. 11bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 12bdd1243dSDimitry Andric 13bdd1243dSDimitry Andric #include "RISCVRegisterBankInfo.h" 14bdd1243dSDimitry Andric #include "MCTargetDesc/RISCVMCTargetDesc.h" 15bdd1243dSDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 16bdd1243dSDimitry Andric #include "llvm/CodeGen/RegisterBank.h" 17bdd1243dSDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 18bdd1243dSDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 19bdd1243dSDimitry Andric 20bdd1243dSDimitry Andric #define GET_TARGET_REGBANK_IMPL 21bdd1243dSDimitry Andric #include "RISCVGenRegisterBank.inc" 22bdd1243dSDimitry Andric 23bdd1243dSDimitry Andric using namespace llvm; 24bdd1243dSDimitry Andric 25*06c3fb27SDimitry Andric RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode) 26*06c3fb27SDimitry Andric : RISCVGenRegisterBankInfo(HwMode) {} 27