1bdd1243dSDimitry Andric//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===// 2bdd1243dSDimitry Andric// 3bdd1243dSDimitry Andric// The LLVM Compiler Infrastructure 4bdd1243dSDimitry Andric// 5bdd1243dSDimitry Andric// This file is distributed under the University of Illinois Open Source 6bdd1243dSDimitry Andric// License. See LICENSE.TXT for details. 7bdd1243dSDimitry Andric// 8bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 9bdd1243dSDimitry Andric// 10bdd1243dSDimitry Andric// This file describes the instructions introduced for the Future CPU. 11bdd1243dSDimitry Andric// 12bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 13bdd1243dSDimitry Andric 14bdd1243dSDimitry Andricclass XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 15bdd1243dSDimitry Andric string asmstr, list<dag> pattern> 16bdd1243dSDimitry Andric : I<opcode, OOL, IOL, asmstr, NoItinerary> { 17bdd1243dSDimitry Andric bits<5> RT; 18bdd1243dSDimitry Andric bits<5> RA; 19bdd1243dSDimitry Andric bits<5> RB; 20bdd1243dSDimitry Andric bit L; 21bdd1243dSDimitry Andric 22bdd1243dSDimitry Andric let Pattern = pattern; 23bdd1243dSDimitry Andric 24bdd1243dSDimitry Andric bit RC = 0; // set by isRecordForm 25bdd1243dSDimitry Andric 26bdd1243dSDimitry Andric let Inst{6-10} = RT; 27bdd1243dSDimitry Andric let Inst{11-15} = RA; 28bdd1243dSDimitry Andric let Inst{16-20} = RB; 29bdd1243dSDimitry Andric let Inst{21} = L; 30bdd1243dSDimitry Andric let Inst{22-30} = xo; 31bdd1243dSDimitry Andric let Inst{31} = RC; 32bdd1243dSDimitry Andric} 33bdd1243dSDimitry Andric 34bdd1243dSDimitry Andricmulticlass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 35bdd1243dSDimitry Andric string asmbase, string asmstr, 36bdd1243dSDimitry Andric list<dag> pattern> { 37bdd1243dSDimitry Andric let BaseName = asmbase in { 38bdd1243dSDimitry Andric def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL, 39bdd1243dSDimitry Andric !strconcat(asmbase, !strconcat(" ", asmstr)), 40bdd1243dSDimitry Andric pattern>, RecFormRel; 41bdd1243dSDimitry Andric let Defs = [CR0] in 42bdd1243dSDimitry Andric def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL, 43bdd1243dSDimitry Andric !strconcat(asmbase, !strconcat(". ", asmstr)), 44bdd1243dSDimitry Andric []>, isRecordForm, RecFormRel; 45bdd1243dSDimitry Andric } 46bdd1243dSDimitry Andric} 47bdd1243dSDimitry Andric 48bdd1243dSDimitry Andriclet Predicates = [IsISAFuture] in { 49bdd1243dSDimitry Andric defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT), 50bdd1243dSDimitry Andric (ins g8rc:$RA, g8rc:$RB, u1imm:$L), 51bdd1243dSDimitry Andric "subfus", "$RT, $L, $RA, $RB", []>; 52bdd1243dSDimitry Andric} 53bdd1243dSDimitry Andric 54bdd1243dSDimitry Andriclet Predicates = [HasVSX, IsISAFuture] in { 55bdd1243dSDimitry Andric let mayLoad = 1 in { 56*06c3fb27SDimitry Andric def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB), 57*06c3fb27SDimitry Andric "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>; 58bdd1243dSDimitry Andric 59*06c3fb27SDimitry Andric def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB), 60*06c3fb27SDimitry Andric "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>; 61bdd1243dSDimitry Andric 62bdd1243dSDimitry Andric def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), 63*06c3fb27SDimitry Andric (ins memr:$RA, g8rc:$RB), 64*06c3fb27SDimitry Andric "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>; 65bdd1243dSDimitry Andric 66bdd1243dSDimitry Andric def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), 67*06c3fb27SDimitry Andric (ins memr:$RA, g8rc:$RB), 68*06c3fb27SDimitry Andric "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>; 69bdd1243dSDimitry Andric } 70bdd1243dSDimitry Andric 71bdd1243dSDimitry Andric let mayStore = 1 in { 72bdd1243dSDimitry Andric def STXVRL : XX1Form_memOp<31, 653, (outs), 73*06c3fb27SDimitry Andric (ins vsrc:$XT, memr:$RA, g8rc:$RB), 74*06c3fb27SDimitry Andric "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>; 75bdd1243dSDimitry Andric 76bdd1243dSDimitry Andric def STXVRLL : XX1Form_memOp<31, 685, (outs), 77*06c3fb27SDimitry Andric (ins vsrc:$XT, memr:$RA, g8rc:$RB), 78*06c3fb27SDimitry Andric "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>; 79bdd1243dSDimitry Andric 80bdd1243dSDimitry Andric def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs), 81*06c3fb27SDimitry Andric (ins vsrprc:$XTp, memr:$RA, g8rc:$RB), 82*06c3fb27SDimitry Andric "stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>; 83bdd1243dSDimitry Andric 84bdd1243dSDimitry Andric def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs), 85*06c3fb27SDimitry Andric (ins vsrprc:$XTp, memr:$RA, g8rc:$RB), 86*06c3fb27SDimitry Andric "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>; 87bdd1243dSDimitry Andric } 88bdd1243dSDimitry Andric} 89