1e8d8bef9SDimitry Andric //===-- PPCRegisterBankInfo.h -----------------------------------*- C++ -*-===// 2e8d8bef9SDimitry Andric // 3e8d8bef9SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric // 7e8d8bef9SDimitry Andric //===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric /// 9e8d8bef9SDimitry Andric /// \file 10e8d8bef9SDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for PowerPC. 11e8d8bef9SDimitry Andric /// 12e8d8bef9SDimitry Andric //===----------------------------------------------------------------------===// 13e8d8bef9SDimitry Andric 14e8d8bef9SDimitry Andric #ifndef LLVM_LIB_TARGET_PPC_GISEL_PPCREGISTERBANKINFO_H 15e8d8bef9SDimitry Andric #define LLVM_LIB_TARGET_PPC_GISEL_PPCREGISTERBANKINFO_H 16e8d8bef9SDimitry Andric 1781ad6265SDimitry Andric #include "llvm/CodeGen/RegisterBank.h" 1881ad6265SDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 19e8d8bef9SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 20e8d8bef9SDimitry Andric 21e8d8bef9SDimitry Andric #define GET_REGBANK_DECLARATIONS 22e8d8bef9SDimitry Andric #include "PPCGenRegisterBank.inc" 23e8d8bef9SDimitry Andric 24e8d8bef9SDimitry Andric namespace llvm { 25e8d8bef9SDimitry Andric class TargetRegisterInfo; 26e8d8bef9SDimitry Andric 27e8d8bef9SDimitry Andric class PPCGenRegisterBankInfo : public RegisterBankInfo { 28e8d8bef9SDimitry Andric protected: 29bdd1243dSDimitry Andric enum PartialMappingIdx { 30bdd1243dSDimitry Andric PMI_None = -1, 31bdd1243dSDimitry Andric PMI_GPR32 = 1, 32bdd1243dSDimitry Andric PMI_GPR64 = 2, 33bdd1243dSDimitry Andric PMI_FPR32 = 3, 34bdd1243dSDimitry Andric PMI_FPR64 = 4, 3506c3fb27SDimitry Andric PMI_VEC128 = 5, 3606c3fb27SDimitry Andric PMI_CR = 6, 37bdd1243dSDimitry Andric PMI_Min = PMI_GPR32, 38bdd1243dSDimitry Andric }; 39bdd1243dSDimitry Andric 40*5f757f3fSDimitry Andric static const RegisterBankInfo::PartialMapping PartMappings[]; 41*5f757f3fSDimitry Andric static const RegisterBankInfo::ValueMapping ValMappings[]; 42*5f757f3fSDimitry Andric static const PartialMappingIdx BankIDToCopyMapIdx[]; 43bdd1243dSDimitry Andric 44bdd1243dSDimitry Andric /// Get the pointer to the ValueMapping representing the RegisterBank 45bdd1243dSDimitry Andric /// at \p RBIdx. 46bdd1243dSDimitry Andric /// 47bdd1243dSDimitry Andric /// The returned mapping works for instructions with the same kind of 48bdd1243dSDimitry Andric /// operands for up to 3 operands. 49bdd1243dSDimitry Andric /// 50bdd1243dSDimitry Andric /// \pre \p RBIdx != PartialMappingIdx::None 51bdd1243dSDimitry Andric static const RegisterBankInfo::ValueMapping * 52bdd1243dSDimitry Andric getValueMapping(PartialMappingIdx RBIdx); 53bdd1243dSDimitry Andric 54bdd1243dSDimitry Andric /// Get the pointer to the ValueMapping of the operands of a copy 55bdd1243dSDimitry Andric /// instruction from the \p SrcBankID register bank to the \p DstBankID 56bdd1243dSDimitry Andric /// register bank with a size of \p Size. 57bdd1243dSDimitry Andric static const RegisterBankInfo::ValueMapping * 58bdd1243dSDimitry Andric getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size); 59bdd1243dSDimitry Andric 60e8d8bef9SDimitry Andric #define GET_TARGET_REGBANK_CLASS 61e8d8bef9SDimitry Andric #include "PPCGenRegisterBank.inc" 62e8d8bef9SDimitry Andric }; 63e8d8bef9SDimitry Andric 64e8d8bef9SDimitry Andric class PPCRegisterBankInfo final : public PPCGenRegisterBankInfo { 65e8d8bef9SDimitry Andric public: 66e8d8bef9SDimitry Andric PPCRegisterBankInfo(const TargetRegisterInfo &TRI); 67bdd1243dSDimitry Andric 68bdd1243dSDimitry Andric const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 69bdd1243dSDimitry Andric LLT Ty) const override; 70bdd1243dSDimitry Andric const InstructionMapping & 71bdd1243dSDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 72bdd1243dSDimitry Andric 73bdd1243dSDimitry Andric InstructionMappings 74bdd1243dSDimitry Andric getInstrAlternativeMappings(const MachineInstr &MI) const override; 75bdd1243dSDimitry Andric 76bdd1243dSDimitry Andric private: 77bdd1243dSDimitry Andric /// Maximum recursion depth for hasFPConstraints. 78bdd1243dSDimitry Andric const unsigned MaxFPRSearchDepth = 2; 79bdd1243dSDimitry Andric 80bdd1243dSDimitry Andric /// \returns true if \p MI only uses and defines FPRs. 81bdd1243dSDimitry Andric bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 82bdd1243dSDimitry Andric const TargetRegisterInfo &TRI, 83bdd1243dSDimitry Andric unsigned Depth = 0) const; 84bdd1243dSDimitry Andric 85bdd1243dSDimitry Andric /// \returns true if \p MI only uses FPRs. 86bdd1243dSDimitry Andric bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 87bdd1243dSDimitry Andric const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 88bdd1243dSDimitry Andric 89bdd1243dSDimitry Andric /// \returns true if \p MI only defines FPRs. 90bdd1243dSDimitry Andric bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 91bdd1243dSDimitry Andric const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 92e8d8bef9SDimitry Andric }; 93e8d8bef9SDimitry Andric } // namespace llvm 94e8d8bef9SDimitry Andric 95e8d8bef9SDimitry Andric #endif 96