1*04eeddc0SDimitry Andric//===-- M68k.td - Motorola 680x0 target definitions --------*- tablegen -*-===// 2fe6060f1SDimitry Andric// 3fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6fe6060f1SDimitry Andric// 7fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 8fe6060f1SDimitry Andric/// 9fe6060f1SDimitry Andric/// \file 10fe6060f1SDimitry Andric/// This is a target description file for the Motorola 680x0 family, referred 11fe6060f1SDimitry Andric/// to here as the "M68k" architecture. 12fe6060f1SDimitry Andric/// 13fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 14fe6060f1SDimitry Andric 15fe6060f1SDimitry Andricinclude "llvm/Target/Target.td" 16fe6060f1SDimitry Andric 17fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 18fe6060f1SDimitry Andric// M68k Subtarget features 19fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 20fe6060f1SDimitry Andric 21fe6060f1SDimitry Andricdef FeatureISA00 22fe6060f1SDimitry Andric : SubtargetFeature<"isa-68000", "SubtargetKind", "M00", 23fe6060f1SDimitry Andric "Is M68000 ISA supported">; 24fe6060f1SDimitry Andric 25fe6060f1SDimitry Andricdef FeatureISA10 26fe6060f1SDimitry Andric : SubtargetFeature<"isa-68010", "SubtargetKind", "M10", 27fe6060f1SDimitry Andric "Is M68010 ISA supported", 28fe6060f1SDimitry Andric [ FeatureISA00 ]>; 29fe6060f1SDimitry Andric 30fe6060f1SDimitry Andricdef FeatureISA20 31fe6060f1SDimitry Andric : SubtargetFeature<"isa-68020", "SubtargetKind", "M20", 32fe6060f1SDimitry Andric "Is M68020 ISA supported", 33fe6060f1SDimitry Andric [ FeatureISA10 ]>; 34fe6060f1SDimitry Andric 35fe6060f1SDimitry Andricdef FeatureISA30 36fe6060f1SDimitry Andric : SubtargetFeature<"isa-68030", "SubtargetKind", "M30", 37fe6060f1SDimitry Andric "Is M68030 ISA supported", 38fe6060f1SDimitry Andric [ FeatureISA20 ]>; 39fe6060f1SDimitry Andric 40fe6060f1SDimitry Andricdef FeatureISA40 41fe6060f1SDimitry Andric : SubtargetFeature<"isa-68040", "SubtargetKind", "M40", 42fe6060f1SDimitry Andric "Is M68040 ISA supported", 43fe6060f1SDimitry Andric [ FeatureISA30 ]>; 44fe6060f1SDimitry Andric 45fe6060f1SDimitry Andricdef FeatureISA60 46fe6060f1SDimitry Andric : SubtargetFeature<"isa-68060", "SubtargetKind", "M60", 47fe6060f1SDimitry Andric "Is M68060 ISA supported", 48fe6060f1SDimitry Andric [ FeatureISA40 ]>; 49fe6060f1SDimitry Andric 50fe6060f1SDimitry Andricforeach i = {0-6} in 51fe6060f1SDimitry Andric def FeatureReserveA#i : 52fe6060f1SDimitry Andric SubtargetFeature<"reserve-a"#i, "UserReservedRegister[M68k::A"#i#"]", 53fe6060f1SDimitry Andric "true", "Reserve A"#i#" register">; 54fe6060f1SDimitry Andricforeach i = {0-7} in 55fe6060f1SDimitry Andric def FeatureReserveD#i : 56fe6060f1SDimitry Andric SubtargetFeature<"reserve-d"#i, "UserReservedRegister[M68k::D"#i#"]", 57fe6060f1SDimitry Andric "true", "Reserve D"#i#" register">; 58fe6060f1SDimitry Andric 59fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 60fe6060f1SDimitry Andric// M68k processors supported. 61fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 62fe6060f1SDimitry Andric 63fe6060f1SDimitry Andricinclude "M68kSchedule.td" 64fe6060f1SDimitry Andric 65fe6060f1SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 66fe6060f1SDimitry Andric : ProcessorModel<Name, GenericM68kModel, Features>; 67fe6060f1SDimitry Andric 68fe6060f1SDimitry Andricdef : Proc<"generic", [ FeatureISA00 ]>; 69fe6060f1SDimitry Andricdef : Proc<"M68000", [ FeatureISA00 ]>; 70fe6060f1SDimitry Andricdef : Proc<"M68010", [ FeatureISA10 ]>; 71fe6060f1SDimitry Andricdef : Proc<"M68020", [ FeatureISA20 ]>; 72fe6060f1SDimitry Andricdef : Proc<"M68030", [ FeatureISA30 ]>; 73fe6060f1SDimitry Andricdef : Proc<"M68040", [ FeatureISA40 ]>; 74fe6060f1SDimitry Andricdef : Proc<"M68060", [ FeatureISA60 ]>; 75fe6060f1SDimitry Andric 76fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 77fe6060f1SDimitry Andric// Register File Description 78fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 79fe6060f1SDimitry Andric 80fe6060f1SDimitry Andricinclude "M68kRegisterInfo.td" 81349cc55cSDimitry Andricinclude "GISel/M68kRegisterBanks.td" 82fe6060f1SDimitry Andric 83fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 84fe6060f1SDimitry Andric// Instruction Descriptions 85fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 86fe6060f1SDimitry Andric 87fe6060f1SDimitry Andricinclude "M68kInstrInfo.td" 88fe6060f1SDimitry Andric 89fe6060f1SDimitry Andricdef M68kInstrInfo : InstrInfo; 90fe6060f1SDimitry Andric 91fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 92fe6060f1SDimitry Andric// Calling Conventions 93fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 94fe6060f1SDimitry Andric 95fe6060f1SDimitry Andricinclude "M68kCallingConv.td" 96fe6060f1SDimitry Andric 97fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 98fe6060f1SDimitry Andric// Assembly Printers 99fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 100fe6060f1SDimitry Andric 101fe6060f1SDimitry Andricdef M68kAsmWriter : AsmWriter { 102fe6060f1SDimitry Andric string AsmWriterClassName = "InstPrinter"; 103fe6060f1SDimitry Andric bit isMCAsmWriter = 1; 104fe6060f1SDimitry Andric} 105fe6060f1SDimitry Andric 106fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 107fe6060f1SDimitry Andric// Assembly Parsers 108fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 109fe6060f1SDimitry Andric 110fe6060f1SDimitry Andricdef M68kAsmParser : AsmParser { 111fe6060f1SDimitry Andric let ShouldEmitMatchRegisterName = 0; 112fe6060f1SDimitry Andric let ShouldEmitMatchRegisterAltName = 0; 113fe6060f1SDimitry Andric} 114fe6060f1SDimitry Andric 115fe6060f1SDimitry Andricdef M68kAsmParserVariant : AsmParserVariant { 116fe6060f1SDimitry Andric int Variant = 0; 117fe6060f1SDimitry Andric} 118fe6060f1SDimitry Andric 119fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 120fe6060f1SDimitry Andric// Target 121fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 122fe6060f1SDimitry Andric 123fe6060f1SDimitry Andricdef M68k : Target { 124fe6060f1SDimitry Andric let InstructionSet = M68kInstrInfo; 125fe6060f1SDimitry Andric let AssemblyParsers = [M68kAsmParser]; 126fe6060f1SDimitry Andric let AssemblyWriters = [M68kAsmWriter]; 127fe6060f1SDimitry Andric} 128