1*81ad6265SDimitry Andric //=- LoongArchMCInstLower.cpp - Convert LoongArch MachineInstr to an MCInst -=// 2*81ad6265SDimitry Andric // 3*81ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*81ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*81ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*81ad6265SDimitry Andric // 7*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 8*81ad6265SDimitry Andric // 9*81ad6265SDimitry Andric // This file contains code to lower LoongArch MachineInstrs to their 10*81ad6265SDimitry Andric // corresponding MCInst records. 11*81ad6265SDimitry Andric // 12*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 13*81ad6265SDimitry Andric 14*81ad6265SDimitry Andric #include "LoongArch.h" 15*81ad6265SDimitry Andric #include "LoongArchSubtarget.h" 16*81ad6265SDimitry Andric #include "llvm/CodeGen/AsmPrinter.h" 17*81ad6265SDimitry Andric #include "llvm/CodeGen/MachineBasicBlock.h" 18*81ad6265SDimitry Andric #include "llvm/CodeGen/MachineInstr.h" 19*81ad6265SDimitry Andric #include "llvm/MC/MCAsmInfo.h" 20*81ad6265SDimitry Andric #include "llvm/MC/MCContext.h" 21*81ad6265SDimitry Andric #include "llvm/Support/raw_ostream.h" 22*81ad6265SDimitry Andric 23*81ad6265SDimitry Andric using namespace llvm; 24*81ad6265SDimitry Andric 25*81ad6265SDimitry Andric bool llvm::lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO, 26*81ad6265SDimitry Andric MCOperand &MCOp, 27*81ad6265SDimitry Andric const AsmPrinter &AP) { 28*81ad6265SDimitry Andric switch (MO.getType()) { 29*81ad6265SDimitry Andric default: 30*81ad6265SDimitry Andric report_fatal_error( 31*81ad6265SDimitry Andric "lowerLoongArchMachineOperandToMCOperand: unknown operand type"); 32*81ad6265SDimitry Andric case MachineOperand::MO_Register: 33*81ad6265SDimitry Andric // Ignore all implicit register operands. 34*81ad6265SDimitry Andric if (MO.isImplicit()) 35*81ad6265SDimitry Andric return false; 36*81ad6265SDimitry Andric MCOp = MCOperand::createReg(MO.getReg()); 37*81ad6265SDimitry Andric break; 38*81ad6265SDimitry Andric case MachineOperand::MO_RegisterMask: 39*81ad6265SDimitry Andric // Regmasks are like implicit defs. 40*81ad6265SDimitry Andric return false; 41*81ad6265SDimitry Andric case MachineOperand::MO_Immediate: 42*81ad6265SDimitry Andric MCOp = MCOperand::createImm(MO.getImm()); 43*81ad6265SDimitry Andric break; 44*81ad6265SDimitry Andric // TODO: lower special operands 45*81ad6265SDimitry Andric case MachineOperand::MO_MachineBasicBlock: 46*81ad6265SDimitry Andric case MachineOperand::MO_GlobalAddress: 47*81ad6265SDimitry Andric case MachineOperand::MO_BlockAddress: 48*81ad6265SDimitry Andric case MachineOperand::MO_ExternalSymbol: 49*81ad6265SDimitry Andric case MachineOperand::MO_ConstantPoolIndex: 50*81ad6265SDimitry Andric case MachineOperand::MO_JumpTableIndex: 51*81ad6265SDimitry Andric break; 52*81ad6265SDimitry Andric } 53*81ad6265SDimitry Andric return true; 54*81ad6265SDimitry Andric } 55*81ad6265SDimitry Andric 56*81ad6265SDimitry Andric bool llvm::lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI, 57*81ad6265SDimitry Andric MCInst &OutMI, AsmPrinter &AP) { 58*81ad6265SDimitry Andric OutMI.setOpcode(MI->getOpcode()); 59*81ad6265SDimitry Andric 60*81ad6265SDimitry Andric for (const MachineOperand &MO : MI->operands()) { 61*81ad6265SDimitry Andric MCOperand MCOp; 62*81ad6265SDimitry Andric if (lowerLoongArchMachineOperandToMCOperand(MO, MCOp, AP)) 63*81ad6265SDimitry Andric OutMI.addOperand(MCOp); 64*81ad6265SDimitry Andric } 65*81ad6265SDimitry Andric return false; 66*81ad6265SDimitry Andric } 67