1*bdd1243dSDimitry Andric//=-HexagonScheduleV71T.td - Hexagon V71 Tiny Core Scheduling Definition ----=// 2*bdd1243dSDimitry Andric// 3*bdd1243dSDimitry Andric// The LLVM Compiler Infrastructure 4*bdd1243dSDimitry Andric// 5*bdd1243dSDimitry Andric// This file is distributed under the University of Illinois Open Source 6*bdd1243dSDimitry Andric// License. See LICENSE.TXT for details. 7*bdd1243dSDimitry Andric// 8*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 9*bdd1243dSDimitry Andric 10*bdd1243dSDimitry Andricclass HexagonV71TPseudoItin { 11*bdd1243dSDimitry Andric list<InstrItinData> V71TPseudoItin_list = [ 12*bdd1243dSDimitry Andric InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1], 13*bdd1243dSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 14*bdd1243dSDimitry Andric InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 15*bdd1243dSDimitry Andric InstrStage<1, [SLOT2, SLOT3]>], 16*bdd1243dSDimitry Andric [2, 1, 1], 17*bdd1243dSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 18*bdd1243dSDimitry Andric InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], 19*bdd1243dSDimitry Andric [2, 1, 1]>, 20*bdd1243dSDimitry Andric InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> 21*bdd1243dSDimitry Andric ]; 22*bdd1243dSDimitry Andric} 23*bdd1243dSDimitry Andric 24*bdd1243dSDimitry Andric// 25*bdd1243dSDimitry Andric// HVXItin contains some old itineraries still used by a handful of 26*bdd1243dSDimitry Andric// instructions. Hopefully, we will be able to get rid of them soon. 27*bdd1243dSDimitry Andricdef HexagonV71TItinList : DepScalarItinV71T, DepHVXItinV71, HVXItin, 28*bdd1243dSDimitry Andric HexagonV71TPseudoItin { 29*bdd1243dSDimitry Andric list<InstrItinData> V71TItin_list = [ 30*bdd1243dSDimitry Andric InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>], 31*bdd1243dSDimitry Andric [3, 1, 1], 32*bdd1243dSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 33*bdd1243dSDimitry Andric InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>], 34*bdd1243dSDimitry Andric [1, 1, 3, 3], 35*bdd1243dSDimitry Andric [Hex_FWD, Hex_FWD]> 36*bdd1243dSDimitry Andric ]; 37*bdd1243dSDimitry Andric list<InstrItinData> ItinList = 38*bdd1243dSDimitry Andric !listconcat(DepScalarItinV71T_list, V71TItin_list, DepHVXItinV71_list, 39*bdd1243dSDimitry Andric HVXItin_list, V71TPseudoItin_list); 40*bdd1243dSDimitry Andric} 41*bdd1243dSDimitry Andric 42*bdd1243dSDimitry Andricdef HexagonItinerariesV71T : 43*bdd1243dSDimitry Andric ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 44*bdd1243dSDimitry Andric CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 45*bdd1243dSDimitry Andric CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 46*bdd1243dSDimitry Andric CVI_ALL_NOMEM, CVI_ZW], 47*bdd1243dSDimitry Andric [Hex_FWD, HVX_FWD], 48*bdd1243dSDimitry Andric HexagonV71TItinList.ItinList>; 49*bdd1243dSDimitry Andric 50*bdd1243dSDimitry Andricdef HexagonModelV71T : SchedMachineModel { 51*bdd1243dSDimitry Andric let IssueWidth = 3; 52*bdd1243dSDimitry Andric let Itineraries = HexagonItinerariesV71T; 53*bdd1243dSDimitry Andric let LoadLatency = 1; 54*bdd1243dSDimitry Andric let CompleteModel = 0; 55*bdd1243dSDimitry Andric} 56*bdd1243dSDimitry Andric 57*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 58*bdd1243dSDimitry Andric// Hexagon V71 Tiny Core Resource Definitions - 59*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 60