1*5ffd83dbSDimitry Andric//=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=// 2*5ffd83dbSDimitry Andric// 3*5ffd83dbSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*5ffd83dbSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*5ffd83dbSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*5ffd83dbSDimitry Andric// 7*5ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 8*5ffd83dbSDimitry Andric 9*5ffd83dbSDimitry Andricclass HexagonV67TPseudoItin { 10*5ffd83dbSDimitry Andric list<InstrItinData> V67TPseudoItin_list = [ 11*5ffd83dbSDimitry Andric InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1], 12*5ffd83dbSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 13*5ffd83dbSDimitry Andric InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 14*5ffd83dbSDimitry Andric InstrStage<1, [SLOT2, SLOT3]>], 15*5ffd83dbSDimitry Andric [2, 1, 1], 16*5ffd83dbSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 17*5ffd83dbSDimitry Andric InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], 18*5ffd83dbSDimitry Andric [2, 1, 1]>, 19*5ffd83dbSDimitry Andric InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> 20*5ffd83dbSDimitry Andric ]; 21*5ffd83dbSDimitry Andric} 22*5ffd83dbSDimitry Andric 23*5ffd83dbSDimitry Andric// V67TItin_list and HVXItin contain some old itineraries 24*5ffd83dbSDimitry Andric// still used by a handful of instructions. Hopefully, we will be able to 25*5ffd83dbSDimitry Andric// get rid of them soon. 26*5ffd83dbSDimitry Andricdef HexagonV67TItinList : DepScalarItinV67T, 27*5ffd83dbSDimitry Andric DepHVXItinV67, HVXItin, HexagonV67TPseudoItin { 28*5ffd83dbSDimitry Andric list<InstrItinData> V67TItin_list = [ 29*5ffd83dbSDimitry Andric InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>], 30*5ffd83dbSDimitry Andric [3, 1, 1], 31*5ffd83dbSDimitry Andric [Hex_FWD, Hex_FWD, Hex_FWD]>, 32*5ffd83dbSDimitry Andric InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>], 33*5ffd83dbSDimitry Andric [1, 1, 3, 3], 34*5ffd83dbSDimitry Andric [Hex_FWD, Hex_FWD]> 35*5ffd83dbSDimitry Andric ]; 36*5ffd83dbSDimitry Andric 37*5ffd83dbSDimitry Andric list<InstrItinData> ItinList = 38*5ffd83dbSDimitry Andric !listconcat(DepScalarItinV67T_list, 39*5ffd83dbSDimitry Andric DepHVXItinV67_list, V67TItin_list, 40*5ffd83dbSDimitry Andric HVXItin_list, V67TPseudoItin_list); 41*5ffd83dbSDimitry Andric} 42*5ffd83dbSDimitry Andric 43*5ffd83dbSDimitry Andricdef HexagonItinerariesV67T : 44*5ffd83dbSDimitry Andric ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 45*5ffd83dbSDimitry Andric CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 46*5ffd83dbSDimitry Andric CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 47*5ffd83dbSDimitry Andric CVI_ALL_NOMEM, CVI_ZW], 48*5ffd83dbSDimitry Andric [Hex_FWD, HVX_FWD], 49*5ffd83dbSDimitry Andric HexagonV67TItinList.ItinList>; 50*5ffd83dbSDimitry Andric 51*5ffd83dbSDimitry Andric 52*5ffd83dbSDimitry Andricdef HexagonModelV67T : SchedMachineModel { 53*5ffd83dbSDimitry Andric let IssueWidth = 3; 54*5ffd83dbSDimitry Andric let Itineraries = HexagonItinerariesV67T; 55*5ffd83dbSDimitry Andric let LoadLatency = 1; 56*5ffd83dbSDimitry Andric let CompleteModel = 0; 57*5ffd83dbSDimitry Andric} 58*5ffd83dbSDimitry Andric 59*5ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 60*5ffd83dbSDimitry Andric// Hexagon V67 Tiny Core Resource Definitions - 61*5ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 62