1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "ARMTargetMachine.h" 13 #include "ARM.h" 14 #include "ARMMacroFusion.h" 15 #include "ARMSubtarget.h" 16 #include "ARMTargetObjectFile.h" 17 #include "ARMTargetTransformInfo.h" 18 #include "MCTargetDesc/ARMMCTargetDesc.h" 19 #include "TargetInfo/ARMTargetInfo.h" 20 #include "llvm/ADT/Optional.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/StringRef.h" 23 #include "llvm/ADT/Triple.h" 24 #include "llvm/Analysis/TargetTransformInfo.h" 25 #include "llvm/CodeGen/ExecutionDomainFix.h" 26 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 30 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 34 #include "llvm/CodeGen/MachineFunction.h" 35 #include "llvm/CodeGen/MachineScheduler.h" 36 #include "llvm/CodeGen/Passes.h" 37 #include "llvm/CodeGen/TargetPassConfig.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/DataLayout.h" 40 #include "llvm/IR/Function.h" 41 #include "llvm/MC/TargetRegistry.h" 42 #include "llvm/Pass.h" 43 #include "llvm/Support/CodeGen.h" 44 #include "llvm/Support/CommandLine.h" 45 #include "llvm/Support/ErrorHandling.h" 46 #include "llvm/Support/TargetParser.h" 47 #include "llvm/Target/TargetLoweringObjectFile.h" 48 #include "llvm/Target/TargetOptions.h" 49 #include "llvm/Transforms/CFGuard.h" 50 #include "llvm/Transforms/IPO.h" 51 #include "llvm/Transforms/Scalar.h" 52 #include <cassert> 53 #include <memory> 54 #include <string> 55 56 using namespace llvm; 57 58 static cl::opt<bool> 59 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, 60 cl::desc("Inhibit optimization of S->D register accesses on A15"), 61 cl::init(false)); 62 63 static cl::opt<bool> 64 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, 65 cl::desc("Run SimplifyCFG after expanding atomic operations" 66 " to make use of cmpxchg flow-based information"), 67 cl::init(true)); 68 69 static cl::opt<bool> 70 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, 71 cl::desc("Enable ARM load/store optimization pass"), 72 cl::init(true)); 73 74 // FIXME: Unify control over GlobalMerge. 75 static cl::opt<cl::boolOrDefault> 76 EnableGlobalMerge("arm-global-merge", cl::Hidden, 77 cl::desc("Enable the global merge pass")); 78 79 namespace llvm { 80 void initializeARMExecutionDomainFixPass(PassRegistry&); 81 } 82 83 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { 84 // Register the target. 85 RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget()); 86 RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget()); 87 RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget()); 88 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget()); 89 90 PassRegistry &Registry = *PassRegistry::getPassRegistry(); 91 initializeGlobalISel(Registry); 92 initializeARMLoadStoreOptPass(Registry); 93 initializeARMPreAllocLoadStoreOptPass(Registry); 94 initializeARMParallelDSPPass(Registry); 95 initializeARMBranchTargetsPass(Registry); 96 initializeARMConstantIslandsPass(Registry); 97 initializeARMExecutionDomainFixPass(Registry); 98 initializeARMExpandPseudoPass(Registry); 99 initializeThumb2SizeReducePass(Registry); 100 initializeMVEVPTBlockPass(Registry); 101 initializeMVETPAndVPTOptimisationsPass(Registry); 102 initializeMVETailPredicationPass(Registry); 103 initializeARMLowOverheadLoopsPass(Registry); 104 initializeARMBlockPlacementPass(Registry); 105 initializeMVEGatherScatterLoweringPass(Registry); 106 initializeARMSLSHardeningPass(Registry); 107 initializeMVELaneInterleavingPass(Registry); 108 } 109 110 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 111 if (TT.isOSBinFormatMachO()) 112 return std::make_unique<TargetLoweringObjectFileMachO>(); 113 if (TT.isOSWindows()) 114 return std::make_unique<TargetLoweringObjectFileCOFF>(); 115 return std::make_unique<ARMElfTargetObjectFile>(); 116 } 117 118 static ARMBaseTargetMachine::ARMABI 119 computeTargetABI(const Triple &TT, StringRef CPU, 120 const TargetOptions &Options) { 121 StringRef ABIName = Options.MCOptions.getABIName(); 122 123 if (ABIName.empty()) 124 ABIName = ARM::computeDefaultTargetABI(TT, CPU); 125 126 if (ABIName == "aapcs16") 127 return ARMBaseTargetMachine::ARM_ABI_AAPCS16; 128 else if (ABIName.startswith("aapcs")) 129 return ARMBaseTargetMachine::ARM_ABI_AAPCS; 130 else if (ABIName.startswith("apcs")) 131 return ARMBaseTargetMachine::ARM_ABI_APCS; 132 133 llvm_unreachable("Unhandled/unknown ABI Name!"); 134 return ARMBaseTargetMachine::ARM_ABI_UNKNOWN; 135 } 136 137 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 138 const TargetOptions &Options, 139 bool isLittle) { 140 auto ABI = computeTargetABI(TT, CPU, Options); 141 std::string Ret; 142 143 if (isLittle) 144 // Little endian. 145 Ret += "e"; 146 else 147 // Big endian. 148 Ret += "E"; 149 150 Ret += DataLayout::getManglingComponent(TT); 151 152 // Pointers are 32 bits and aligned to 32 bits. 153 Ret += "-p:32:32"; 154 155 // Function pointers are aligned to 8 bits (because the LSB stores the 156 // ARM/Thumb state). 157 Ret += "-Fi8"; 158 159 // ABIs other than APCS have 64 bit integers with natural alignment. 160 if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS) 161 Ret += "-i64:64"; 162 163 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32 164 // bits, others to 64 bits. We always try to align to 64 bits. 165 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS) 166 Ret += "-f64:32:64"; 167 168 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others 169 // to 64. We always ty to give them natural alignment. 170 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS) 171 Ret += "-v64:32:64-v128:32:128"; 172 else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16) 173 Ret += "-v128:64:128"; 174 175 // Try to align aggregates to 32 bits (the default is 64 bits, which has no 176 // particular hardware support on 32-bit ARM). 177 Ret += "-a:0:32"; 178 179 // Integer registers are 32 bits. 180 Ret += "-n32"; 181 182 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit 183 // aligned everywhere else. 184 if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16) 185 Ret += "-S128"; 186 else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS) 187 Ret += "-S64"; 188 else 189 Ret += "-S32"; 190 191 return Ret; 192 } 193 194 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 195 Optional<Reloc::Model> RM) { 196 if (!RM.hasValue()) 197 // Default relocation model on Darwin is PIC. 198 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static; 199 200 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI) 201 assert(TT.isOSBinFormatELF() && 202 "ROPI/RWPI currently only supported for ELF"); 203 204 // DynamicNoPIC is only used on darwin. 205 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin()) 206 return Reloc::Static; 207 208 return *RM; 209 } 210 211 /// Create an ARM architecture model. 212 /// 213 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, 214 StringRef CPU, StringRef FS, 215 const TargetOptions &Options, 216 Optional<Reloc::Model> RM, 217 Optional<CodeModel::Model> CM, 218 CodeGenOpt::Level OL, bool isLittle) 219 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 220 CPU, FS, Options, getEffectiveRelocModel(TT, RM), 221 getEffectiveCodeModel(CM, CodeModel::Small), OL), 222 TargetABI(computeTargetABI(TT, CPU, Options)), 223 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { 224 225 // Default to triple-appropriate float ABI 226 if (Options.FloatABIType == FloatABI::Default) { 227 if (isTargetHardFloat()) 228 this->Options.FloatABIType = FloatABI::Hard; 229 else 230 this->Options.FloatABIType = FloatABI::Soft; 231 } 232 233 // Default to triple-appropriate EABI 234 if (Options.EABIVersion == EABI::Default || 235 Options.EABIVersion == EABI::Unknown) { 236 // musl is compatible with glibc with regard to EABI version 237 if ((TargetTriple.getEnvironment() == Triple::GNUEABI || 238 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 239 TargetTriple.getEnvironment() == Triple::MuslEABI || 240 TargetTriple.getEnvironment() == Triple::MuslEABIHF) && 241 !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin())) 242 this->Options.EABIVersion = EABI::GNU; 243 else 244 this->Options.EABIVersion = EABI::EABI5; 245 } 246 247 if (TT.isOSBinFormatMachO()) { 248 this->Options.TrapUnreachable = true; 249 this->Options.NoTrapAfterNoreturn = true; 250 } 251 252 // ARM supports the debug entry values. 253 setSupportsDebugEntryValues(true); 254 255 initAsmInfo(); 256 257 // ARM supports the MachineOutliner. 258 setMachineOutliner(true); 259 setSupportsDefaultOutlining(true); 260 } 261 262 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default; 263 264 const ARMSubtarget * 265 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { 266 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 267 Attribute FSAttr = F.getFnAttribute("target-features"); 268 269 std::string CPU = 270 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 271 std::string FS = 272 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 273 274 // FIXME: This is related to the code below to reset the target options, 275 // we need to know whether or not the soft float flag is set on the 276 // function before we can generate a subtarget. We also need to use 277 // it as a key for the subtarget since that can be the only difference 278 // between two functions. 279 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 280 // If the soft float attribute is set on the function turn on the soft float 281 // subtarget feature. 282 if (SoftFloat) 283 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 284 285 // Use the optminsize to identify the subtarget, but don't use it in the 286 // feature string. 287 std::string Key = CPU + FS; 288 if (F.hasMinSize()) 289 Key += "+minsize"; 290 291 auto &I = SubtargetMap[Key]; 292 if (!I) { 293 // This needs to be done before we create a new subtarget since any 294 // creation will depend on the TM and the code generation flags on the 295 // function that reside in TargetOptions. 296 resetTargetOptions(F); 297 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle, 298 F.hasMinSize()); 299 300 if (!I->isThumb() && !I->hasARMOps()) 301 F.getContext().emitError("Function '" + F.getName() + "' uses ARM " 302 "instructions, but the target does not support ARM mode execution."); 303 } 304 305 return I.get(); 306 } 307 308 TargetTransformInfo 309 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) { 310 return TargetTransformInfo(ARMTTIImpl(this, F)); 311 } 312 313 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT, 314 StringRef CPU, StringRef FS, 315 const TargetOptions &Options, 316 Optional<Reloc::Model> RM, 317 Optional<CodeModel::Model> CM, 318 CodeGenOpt::Level OL, bool JIT) 319 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 320 321 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT, 322 StringRef CPU, StringRef FS, 323 const TargetOptions &Options, 324 Optional<Reloc::Model> RM, 325 Optional<CodeModel::Model> CM, 326 CodeGenOpt::Level OL, bool JIT) 327 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 328 329 namespace { 330 331 /// ARM Code Generator Pass Configuration Options. 332 class ARMPassConfig : public TargetPassConfig { 333 public: 334 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM) 335 : TargetPassConfig(TM, PM) {} 336 337 ARMBaseTargetMachine &getARMTargetMachine() const { 338 return getTM<ARMBaseTargetMachine>(); 339 } 340 341 ScheduleDAGInstrs * 342 createMachineScheduler(MachineSchedContext *C) const override { 343 ScheduleDAGMILive *DAG = createGenericSchedLive(C); 344 // add DAG Mutations here. 345 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); 346 if (ST.hasFusion()) 347 DAG->addMutation(createARMMacroFusionDAGMutation()); 348 return DAG; 349 } 350 351 ScheduleDAGInstrs * 352 createPostMachineScheduler(MachineSchedContext *C) const override { 353 ScheduleDAGMI *DAG = createGenericSchedPostRA(C); 354 // add DAG Mutations here. 355 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); 356 if (ST.hasFusion()) 357 DAG->addMutation(createARMMacroFusionDAGMutation()); 358 return DAG; 359 } 360 361 void addIRPasses() override; 362 void addCodeGenPrepare() override; 363 bool addPreISel() override; 364 bool addInstSelector() override; 365 bool addIRTranslator() override; 366 bool addLegalizeMachineIR() override; 367 bool addRegBankSelect() override; 368 bool addGlobalInstructionSelect() override; 369 void addPreRegAlloc() override; 370 void addPreSched2() override; 371 void addPreEmitPass() override; 372 void addPreEmitPass2() override; 373 374 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 375 }; 376 377 class ARMExecutionDomainFix : public ExecutionDomainFix { 378 public: 379 static char ID; 380 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {} 381 StringRef getPassName() const override { 382 return "ARM Execution Domain Fix"; 383 } 384 }; 385 char ARMExecutionDomainFix::ID; 386 387 } // end anonymous namespace 388 389 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", 390 "ARM Execution Domain Fix", false, false) 391 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis) 392 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix", 393 "ARM Execution Domain Fix", false, false) 394 395 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) { 396 return new ARMPassConfig(*this, PM); 397 } 398 399 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const { 400 return getStandardCSEConfigForOpt(TM->getOptLevel()); 401 } 402 403 void ARMPassConfig::addIRPasses() { 404 if (TM->Options.ThreadModel == ThreadModel::Single) 405 addPass(createLowerAtomicPass()); 406 else 407 addPass(createAtomicExpandPass()); 408 409 // Cmpxchg instructions are often used with a subsequent comparison to 410 // determine whether it succeeded. We can exploit existing control-flow in 411 // ldrex/strex loops to simplify this, but it needs tidying up. 412 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) 413 addPass(createCFGSimplificationPass( 414 SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true), 415 [this](const Function &F) { 416 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F); 417 return ST.hasAnyDataBarrier() && !ST.isThumb1Only(); 418 })); 419 420 addPass(createMVEGatherScatterLoweringPass()); 421 addPass(createMVELaneInterleavingPass()); 422 423 TargetPassConfig::addIRPasses(); 424 425 // Run the parallel DSP pass. 426 if (getOptLevel() == CodeGenOpt::Aggressive) 427 addPass(createARMParallelDSPPass()); 428 429 // Match interleaved memory accesses to ldN/stN intrinsics. 430 if (TM->getOptLevel() != CodeGenOpt::None) 431 addPass(createInterleavedAccessPass()); 432 433 // Add Control Flow Guard checks. 434 if (TM->getTargetTriple().isOSWindows()) 435 addPass(createCFGuardCheckPass()); 436 } 437 438 void ARMPassConfig::addCodeGenPrepare() { 439 if (getOptLevel() != CodeGenOpt::None) 440 addPass(createTypePromotionPass()); 441 TargetPassConfig::addCodeGenPrepare(); 442 } 443 444 bool ARMPassConfig::addPreISel() { 445 if ((TM->getOptLevel() != CodeGenOpt::None && 446 EnableGlobalMerge == cl::BOU_UNSET) || 447 EnableGlobalMerge == cl::BOU_TRUE) { 448 // FIXME: This is using the thumb1 only constant value for 449 // maximal global offset for merging globals. We may want 450 // to look into using the old value for non-thumb1 code of 451 // 4095 based on the TargetMachine, but this starts to become 452 // tricky when doing code gen per function. 453 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && 454 (EnableGlobalMerge == cl::BOU_UNSET); 455 // Merging of extern globals is enabled by default on non-Mach-O as we 456 // expect it to be generally either beneficial or harmless. On Mach-O it 457 // is disabled as we emit the .subsections_via_symbols directive which 458 // means that merging extern globals is not safe. 459 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO(); 460 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize, 461 MergeExternalByDefault)); 462 } 463 464 if (TM->getOptLevel() != CodeGenOpt::None) { 465 addPass(createHardwareLoopsPass()); 466 addPass(createMVETailPredicationPass()); 467 // FIXME: IR passes can delete address-taken basic blocks, deleting 468 // corresponding blockaddresses. ARMConstantPoolConstant holds references to 469 // address-taken basic blocks which can be invalidated if the function 470 // containing the blockaddress has already been codegen'd and the basic 471 // block is removed. Work around this by forcing all IR passes to run before 472 // any ISel takes place. We should have a more principled way of handling 473 // this. See D99707 for more details. 474 addPass(createBarrierNoopPass()); 475 } 476 477 return false; 478 } 479 480 bool ARMPassConfig::addInstSelector() { 481 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); 482 return false; 483 } 484 485 bool ARMPassConfig::addIRTranslator() { 486 addPass(new IRTranslator(getOptLevel())); 487 return false; 488 } 489 490 bool ARMPassConfig::addLegalizeMachineIR() { 491 addPass(new Legalizer()); 492 return false; 493 } 494 495 bool ARMPassConfig::addRegBankSelect() { 496 addPass(new RegBankSelect()); 497 return false; 498 } 499 500 bool ARMPassConfig::addGlobalInstructionSelect() { 501 addPass(new InstructionSelect(getOptLevel())); 502 return false; 503 } 504 505 void ARMPassConfig::addPreRegAlloc() { 506 if (getOptLevel() != CodeGenOpt::None) { 507 addPass(createMVETPAndVPTOptimisationsPass()); 508 509 addPass(createMLxExpansionPass()); 510 511 if (EnableARMLoadStoreOpt) 512 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true)); 513 514 if (!DisableA15SDOptimization) 515 addPass(createA15SDOptimizerPass()); 516 } 517 } 518 519 void ARMPassConfig::addPreSched2() { 520 if (getOptLevel() != CodeGenOpt::None) { 521 if (EnableARMLoadStoreOpt) 522 addPass(createARMLoadStoreOptimizationPass()); 523 524 addPass(new ARMExecutionDomainFix()); 525 addPass(createBreakFalseDeps()); 526 } 527 528 // Expand some pseudo instructions into multiple instructions to allow 529 // proper scheduling. 530 addPass(createARMExpandPseudoPass()); 531 532 if (getOptLevel() != CodeGenOpt::None) { 533 // When optimising for size, always run the Thumb2SizeReduction pass before 534 // IfConversion. Otherwise, check whether IT blocks are restricted 535 // (e.g. in v8, IfConversion depends on Thumb instruction widths) 536 addPass(createThumb2SizeReductionPass([this](const Function &F) { 537 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() || 538 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT(); 539 })); 540 541 addPass(createIfConverter([](const MachineFunction &MF) { 542 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 543 })); 544 } 545 addPass(createThumb2ITBlockPass()); 546 547 // Add both scheduling passes to give the subtarget an opportunity to pick 548 // between them. 549 if (getOptLevel() != CodeGenOpt::None) { 550 addPass(&PostMachineSchedulerID); 551 addPass(&PostRASchedulerID); 552 } 553 554 addPass(createMVEVPTBlockPass()); 555 addPass(createARMIndirectThunks()); 556 addPass(createARMSLSHardeningPass()); 557 } 558 559 void ARMPassConfig::addPreEmitPass() { 560 addPass(createThumb2SizeReductionPass()); 561 562 // Constant island pass work on unbundled instructions. 563 addPass(createUnpackMachineBundles([](const MachineFunction &MF) { 564 return MF.getSubtarget<ARMSubtarget>().isThumb2(); 565 })); 566 567 // Don't optimize barriers or block placement at -O0. 568 if (getOptLevel() != CodeGenOpt::None) { 569 addPass(createARMBlockPlacementPass()); 570 addPass(createARMOptimizeBarriersPass()); 571 } 572 } 573 574 void ARMPassConfig::addPreEmitPass2() { 575 addPass(createARMBranchTargetsPass()); 576 addPass(createARMConstantIslandPass()); 577 addPass(createARMLowOverheadLoopsPass()); 578 579 if (TM->getTargetTriple().isOSWindows()) { 580 // Identify valid longjmp targets for Windows Control Flow Guard. 581 addPass(createCFGuardLongjmpPass()); 582 // Identify valid eh continuation targets for Windows EHCont Guard. 583 addPass(createEHContGuardCatchretPass()); 584 } 585 } 586