1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Base ARM implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include <array> 25 #include <cstdint> 26 27 #define GET_INSTRINFO_HEADER 28 #include "ARMGenInstrInfo.inc" 29 30 namespace llvm { 31 32 class ARMBaseRegisterInfo; 33 class ARMSubtarget; 34 35 class ARMBaseInstrInfo : public ARMGenInstrInfo { 36 const ARMSubtarget &Subtarget; 37 38 protected: 39 // Can be only subclassed. 40 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 41 42 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, 43 unsigned LoadImmOpc, unsigned LoadOpc) const; 44 45 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 46 /// and \p DefIdx. 47 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 48 /// the list is modeled as <Reg:SubReg, SubIdx>. 49 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 50 /// two elements: 51 /// - %1:sub1, sub0 52 /// - %2<:0>, sub1 53 /// 54 /// \returns true if it is possible to build such an input sequence 55 /// with the pair \p MI, \p DefIdx. False otherwise. 56 /// 57 /// \pre MI.isRegSequenceLike(). 58 bool getRegSequenceLikeInputs( 59 const MachineInstr &MI, unsigned DefIdx, 60 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override; 61 62 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 63 /// and \p DefIdx. 64 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 65 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 66 /// - %1:sub1, sub0 67 /// 68 /// \returns true if it is possible to build such an input sequence 69 /// with the pair \p MI, \p DefIdx. False otherwise. 70 /// 71 /// \pre MI.isExtractSubregLike(). 72 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 73 RegSubRegPairAndIdx &InputReg) const override; 74 75 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 76 /// and \p DefIdx. 77 /// \p [out] BaseReg and \p [out] InsertedReg contain 78 /// the equivalent inputs of INSERT_SUBREG. 79 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 80 /// - BaseReg: %0:sub0 81 /// - InsertedReg: %1:sub1, sub3 82 /// 83 /// \returns true if it is possible to build such an input sequence 84 /// with the pair \p MI, \p DefIdx. False otherwise. 85 /// 86 /// \pre MI.isInsertSubregLike(). 87 bool 88 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 89 RegSubRegPair &BaseReg, 90 RegSubRegPairAndIdx &InsertedReg) const override; 91 92 /// Commutes the operands in the given instruction. 93 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 94 /// 95 /// Do not call this method for a non-commutable instruction or for 96 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 97 /// Even though the instruction is commutable, the method may still 98 /// fail to commute the operands, null pointer is returned in such cases. 99 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 100 unsigned OpIdx1, 101 unsigned OpIdx2) const override; 102 103 /// If the specific machine instruction is a instruction that moves/copies 104 /// value from one register to another register return true along with 105 /// @Source machine operand and @Destination machine operand. 106 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, 107 const MachineOperand *&Destination) const override; 108 109 public: 110 // Return whether the target has an explicit NOP encoding. 111 bool hasNOP() const; 112 113 // Return the non-pre/post incrementing version of 'Opc'. Return 0 114 // if there is not such an opcode. 115 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0; 116 117 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 118 MachineInstr &MI, 119 LiveVariables *LV) const override; 120 121 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 122 const ARMSubtarget &getSubtarget() const { return Subtarget; } 123 124 ScheduleHazardRecognizer * 125 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 126 const ScheduleDAG *DAG) const override; 127 128 ScheduleHazardRecognizer * 129 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 130 const ScheduleDAG *DAG) const override; 131 132 // Branch analysis. 133 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 134 MachineBasicBlock *&FBB, 135 SmallVectorImpl<MachineOperand> &Cond, 136 bool AllowModify = false) const override; 137 unsigned removeBranch(MachineBasicBlock &MBB, 138 int *BytesRemoved = nullptr) const override; 139 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 140 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 141 const DebugLoc &DL, 142 int *BytesAdded = nullptr) const override; 143 144 bool 145 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 146 147 // Predication support. 148 bool isPredicated(const MachineInstr &MI) const override; 149 150 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { 151 int PIdx = MI.findFirstPredOperandIdx(); 152 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() 153 : ARMCC::AL; 154 } 155 156 bool PredicateInstruction(MachineInstr &MI, 157 ArrayRef<MachineOperand> Pred) const override; 158 159 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 160 ArrayRef<MachineOperand> Pred2) const override; 161 162 bool DefinesPredicate(MachineInstr &MI, 163 std::vector<MachineOperand> &Pred) const override; 164 165 bool isPredicable(const MachineInstr &MI) const override; 166 167 // CPSR defined in instruction 168 static bool isCPSRDefined(const MachineInstr &MI); 169 bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const; 170 bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const; 171 172 // Load, scaled register offset 173 bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const; 174 // Load, scaled register offset, not plus LSL2 175 bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const; 176 // Minus reg for ldstso addr mode 177 bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const; 178 // Scaled register offset in address mode 2 179 bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const; 180 // Load multiple, base reg in list 181 bool isLDMBaseRegInList(const MachineInstr &MI) const; 182 // get LDM variable defs size 183 unsigned getLDMVariableDefsSize(const MachineInstr &MI) const; 184 185 /// GetInstSize - Returns the size of the specified MachineInstr. 186 /// 187 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 188 189 unsigned isLoadFromStackSlot(const MachineInstr &MI, 190 int &FrameIndex) const override; 191 unsigned isStoreToStackSlot(const MachineInstr &MI, 192 int &FrameIndex) const override; 193 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 194 int &FrameIndex) const override; 195 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 196 int &FrameIndex) const override; 197 198 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 199 unsigned SrcReg, bool KillSrc, 200 const ARMSubtarget &Subtarget) const; 201 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 202 unsigned DestReg, bool KillSrc, 203 const ARMSubtarget &Subtarget) const; 204 205 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 206 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 207 bool KillSrc) const override; 208 209 void storeRegToStackSlot(MachineBasicBlock &MBB, 210 MachineBasicBlock::iterator MBBI, 211 unsigned SrcReg, bool isKill, int FrameIndex, 212 const TargetRegisterClass *RC, 213 const TargetRegisterInfo *TRI) const override; 214 215 void loadRegFromStackSlot(MachineBasicBlock &MBB, 216 MachineBasicBlock::iterator MBBI, 217 unsigned DestReg, int FrameIndex, 218 const TargetRegisterClass *RC, 219 const TargetRegisterInfo *TRI) const override; 220 221 bool expandPostRAPseudo(MachineInstr &MI) const override; 222 223 bool shouldSink(const MachineInstr &MI) const override; 224 225 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 226 unsigned DestReg, unsigned SubIdx, 227 const MachineInstr &Orig, 228 const TargetRegisterInfo &TRI) const override; 229 230 MachineInstr & 231 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, 232 const MachineInstr &Orig) const override; 233 234 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 235 unsigned SubIdx, unsigned State, 236 const TargetRegisterInfo *TRI) const; 237 238 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, 239 const MachineRegisterInfo *MRI) const override; 240 241 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 242 /// determine if two loads are loading from the same base address. It should 243 /// only return true if the base pointers are the same and the only 244 /// differences between the two addresses is the offset. It also returns the 245 /// offsets by reference. 246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 247 int64_t &Offset2) const override; 248 249 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 250 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 251 /// should be scheduled togther. On some targets if two loads are loading from 252 /// addresses in the same cache line, it's better if they are scheduled 253 /// together. This function takes two integers that represent the load offsets 254 /// from the common base address. It returns true if it decides it's desirable 255 /// to schedule the two loads together. "NumLoads" is the number of loads that 256 /// have already been scheduled after Load1. 257 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 258 int64_t Offset1, int64_t Offset2, 259 unsigned NumLoads) const override; 260 261 bool isSchedulingBoundary(const MachineInstr &MI, 262 const MachineBasicBlock *MBB, 263 const MachineFunction &MF) const override; 264 265 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 266 unsigned NumCycles, unsigned ExtraPredCycles, 267 BranchProbability Probability) const override; 268 269 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 270 unsigned ExtraT, MachineBasicBlock &FMBB, 271 unsigned NumF, unsigned ExtraF, 272 BranchProbability Probability) const override; 273 274 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 275 BranchProbability Probability) const override { 276 return NumCycles == 1; 277 } 278 279 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 280 unsigned NumInsts) const override; 281 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override; 282 283 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 284 MachineBasicBlock &FMBB) const override; 285 286 /// analyzeCompare - For a comparison instruction, return the source registers 287 /// in SrcReg and SrcReg2 if having two register operands, and the value it 288 /// compares against in CmpValue. Return true if the comparison instruction 289 /// can be analyzed. 290 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 291 unsigned &SrcReg2, int &CmpMask, 292 int &CmpValue) const override; 293 294 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 295 /// that we can remove a "comparison with zero"; Remove a redundant CMP 296 /// instruction if the flags can be updated in the same way by an earlier 297 /// instruction such as SUB. 298 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 299 unsigned SrcReg2, int CmpMask, int CmpValue, 300 const MachineRegisterInfo *MRI) const override; 301 302 bool analyzeSelect(const MachineInstr &MI, 303 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 304 unsigned &FalseOp, bool &Optimizable) const override; 305 306 MachineInstr *optimizeSelect(MachineInstr &MI, 307 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 308 bool) const override; 309 310 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 311 /// instruction, try to fold the immediate into the use instruction. 312 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 313 MachineRegisterInfo *MRI) const override; 314 315 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 316 const MachineInstr &MI) const override; 317 318 int getOperandLatency(const InstrItineraryData *ItinData, 319 const MachineInstr &DefMI, unsigned DefIdx, 320 const MachineInstr &UseMI, 321 unsigned UseIdx) const override; 322 int getOperandLatency(const InstrItineraryData *ItinData, 323 SDNode *DefNode, unsigned DefIdx, 324 SDNode *UseNode, unsigned UseIdx) const override; 325 326 /// VFP/NEON execution domains. 327 std::pair<uint16_t, uint16_t> 328 getExecutionDomain(const MachineInstr &MI) const override; 329 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 330 331 unsigned 332 getPartialRegUpdateClearance(const MachineInstr &, unsigned, 333 const TargetRegisterInfo *) const override; 334 void breakPartialRegDependency(MachineInstr &, unsigned, 335 const TargetRegisterInfo *TRI) const override; 336 337 /// Get the number of addresses by LDM or VLDM or zero for unknown. 338 unsigned getNumLDMAddresses(const MachineInstr &MI) const; 339 340 std::pair<unsigned, unsigned> 341 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 342 ArrayRef<std::pair<unsigned, const char *>> 343 getSerializableDirectMachineOperandTargetFlags() const override; 344 ArrayRef<std::pair<unsigned, const char *>> 345 getSerializableBitmaskMachineOperandTargetFlags() const override; 346 347 private: 348 unsigned getInstBundleLength(const MachineInstr &MI) const; 349 350 int getVLDMDefCycle(const InstrItineraryData *ItinData, 351 const MCInstrDesc &DefMCID, 352 unsigned DefClass, 353 unsigned DefIdx, unsigned DefAlign) const; 354 int getLDMDefCycle(const InstrItineraryData *ItinData, 355 const MCInstrDesc &DefMCID, 356 unsigned DefClass, 357 unsigned DefIdx, unsigned DefAlign) const; 358 int getVSTMUseCycle(const InstrItineraryData *ItinData, 359 const MCInstrDesc &UseMCID, 360 unsigned UseClass, 361 unsigned UseIdx, unsigned UseAlign) const; 362 int getSTMUseCycle(const InstrItineraryData *ItinData, 363 const MCInstrDesc &UseMCID, 364 unsigned UseClass, 365 unsigned UseIdx, unsigned UseAlign) const; 366 int getOperandLatency(const InstrItineraryData *ItinData, 367 const MCInstrDesc &DefMCID, 368 unsigned DefIdx, unsigned DefAlign, 369 const MCInstrDesc &UseMCID, 370 unsigned UseIdx, unsigned UseAlign) const; 371 372 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 373 const MachineInstr &DefMI, unsigned DefIdx, 374 const MCInstrDesc &DefMCID, unsigned DefAdj, 375 const MachineOperand &DefMO, unsigned Reg, 376 const MachineInstr &UseMI, unsigned UseIdx, 377 const MCInstrDesc &UseMCID, unsigned UseAdj) const; 378 379 unsigned getPredicationCost(const MachineInstr &MI) const override; 380 381 unsigned getInstrLatency(const InstrItineraryData *ItinData, 382 const MachineInstr &MI, 383 unsigned *PredCost = nullptr) const override; 384 385 int getInstrLatency(const InstrItineraryData *ItinData, 386 SDNode *Node) const override; 387 388 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 389 const MachineRegisterInfo *MRI, 390 const MachineInstr &DefMI, unsigned DefIdx, 391 const MachineInstr &UseMI, 392 unsigned UseIdx) const override; 393 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 394 const MachineInstr &DefMI, 395 unsigned DefIdx) const override; 396 397 /// verifyInstruction - Perform target specific instruction verification. 398 bool verifyInstruction(const MachineInstr &MI, 399 StringRef &ErrInfo) const override; 400 401 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0; 402 403 void expandMEMCPY(MachineBasicBlock::iterator) const; 404 405 /// Identify instructions that can be folded into a MOVCC instruction, and 406 /// return the defining instruction. 407 MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, 408 const TargetInstrInfo *TII) const; 409 410 private: 411 /// Modeling special VFP / NEON fp MLA / MLS hazards. 412 413 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 414 /// MLx table. 415 DenseMap<unsigned, unsigned> MLxEntryMap; 416 417 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 418 /// stalls when scheduled together with fp MLA / MLS opcodes. 419 SmallSet<unsigned, 16> MLxHazardOpcodes; 420 421 public: 422 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 423 /// instruction. 424 bool isFpMLxInstruction(unsigned Opcode) const { 425 return MLxEntryMap.count(Opcode); 426 } 427 428 /// isFpMLxInstruction - This version also returns the multiply opcode and the 429 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 430 /// the MLX instructions with an extra lane operand. 431 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 432 unsigned &AddSubOpc, bool &NegAcc, 433 bool &HasLane) const; 434 435 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 436 /// will cause stalls when scheduled after (within 4-cycle window) a fp 437 /// MLA / MLS instruction. 438 bool canCauseFpMLxStall(unsigned Opcode) const { 439 return MLxHazardOpcodes.count(Opcode); 440 } 441 442 /// Returns true if the instruction has a shift by immediate that can be 443 /// executed in one cycle less. 444 bool isSwiftFastImmShift(const MachineInstr *MI) const; 445 446 /// Returns predicate register associated with the given frame instruction. 447 unsigned getFramePred(const MachineInstr &MI) const { 448 assert(isFrameInstr(MI)); 449 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP: 450 // - argument declared in the pattern: 451 // 0 - frame size 452 // 1 - arg of CALLSEQ_START/CALLSEQ_END 453 // 2 - predicate code (like ARMCC::AL) 454 // - added by predOps: 455 // 3 - predicate reg 456 return MI.getOperand(3).getReg(); 457 } 458 }; 459 460 /// Get the operands corresponding to the given \p Pred value. By default, the 461 /// predicate register is assumed to be 0 (no register), but you can pass in a 462 /// \p PredReg if that is not the case. 463 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, 464 unsigned PredReg = 0) { 465 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)), 466 MachineOperand::CreateReg(PredReg, false)}}; 467 } 468 469 /// Get the operand corresponding to the conditional code result. By default, 470 /// this is 0 (no register). 471 static inline MachineOperand condCodeOp(unsigned CCReg = 0) { 472 return MachineOperand::CreateReg(CCReg, false); 473 } 474 475 /// Get the operand corresponding to the conditional code result for Thumb1. 476 /// This operand will always refer to CPSR and it will have the Define flag set. 477 /// You can optionally set the Dead flag by means of \p isDead. 478 static inline MachineOperand t1CondCodeOp(bool isDead = false) { 479 return MachineOperand::CreateReg(ARM::CPSR, 480 /*Define*/ true, /*Implicit*/ false, 481 /*Kill*/ false, isDead); 482 } 483 484 static inline 485 bool isUncondBranchOpcode(int Opc) { 486 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 487 } 488 489 static inline bool isVPTOpcode(int Opc) { 490 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || 491 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || 492 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || 493 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || 494 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || 495 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || 496 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || 497 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || 498 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r || 499 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r || 500 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r || 501 Opc == ARM::MVE_VPST; 502 } 503 504 static inline 505 bool isCondBranchOpcode(int Opc) { 506 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 507 } 508 509 static inline bool isJumpTableBranchOpcode(int Opc) { 510 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || 511 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || 512 Opc == ARM::t2BR_JT; 513 } 514 515 static inline 516 bool isIndirectBranchOpcode(int Opc) { 517 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 518 } 519 520 static inline bool isPopOpcode(int Opc) { 521 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 522 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 523 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 524 } 525 526 static inline bool isPushOpcode(int Opc) { 527 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 528 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 529 } 530 531 /// isValidCoprocessorNumber - decide whether an explicit coprocessor 532 /// number is legal in generic instructions like CDP. The answer can 533 /// vary with the subtarget. 534 static inline bool isValidCoprocessorNumber(unsigned Num, 535 const FeatureBitset& featureBits) { 536 // Armv8-A disallows everything *other* than 111x (CP14 and CP15). 537 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE) 538 return false; 539 540 // Armv7 disallows 101x (CP10 and CP11), which clash with VFP/NEON. 541 if (featureBits[ARM::HasV7Ops] && (Num & 0xE) == 0xA) 542 return false; 543 544 // Armv8.1-M also disallows 100x (CP8,CP9) and 111x (CP14,CP15) 545 // which clash with MVE. 546 if (featureBits[ARM::HasV8_1MMainlineOps] && 547 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) 548 return false; 549 550 return true; 551 } 552 553 /// getInstrPredicate - If instruction is predicated, returns its predicate 554 /// condition, otherwise returns AL. It also returns the condition code 555 /// register by reference. 556 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg); 557 558 unsigned getMatchingCondBranchOpcode(unsigned Opc); 559 560 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 561 /// the instruction is encoded with an 'S' bit is determined by the optional 562 /// CPSR def operand. 563 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 564 565 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 566 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 567 /// code. 568 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 569 MachineBasicBlock::iterator &MBBI, 570 const DebugLoc &dl, unsigned DestReg, 571 unsigned BaseReg, int NumBytes, 572 ARMCC::CondCodes Pred, unsigned PredReg, 573 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 574 575 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 576 MachineBasicBlock::iterator &MBBI, 577 const DebugLoc &dl, unsigned DestReg, 578 unsigned BaseReg, int NumBytes, 579 ARMCC::CondCodes Pred, unsigned PredReg, 580 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 581 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 582 MachineBasicBlock::iterator &MBBI, 583 const DebugLoc &dl, unsigned DestReg, 584 unsigned BaseReg, int NumBytes, 585 const TargetInstrInfo &TII, 586 const ARMBaseRegisterInfo &MRI, 587 unsigned MIFlags = 0); 588 589 /// Tries to add registers to the reglist of a given base-updating 590 /// push/pop instruction to adjust the stack by an additional 591 /// NumBytes. This can save a few bytes per function in code-size, but 592 /// obviously generates more memory traffic. As such, it only takes 593 /// effect in functions being optimised for size. 594 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 595 MachineFunction &MF, MachineInstr *MI, 596 unsigned NumBytes); 597 598 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 599 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 600 /// offset could not be handled directly in MI, and return the left-over 601 /// portion by reference. 602 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 603 unsigned FrameReg, int &Offset, 604 const ARMBaseInstrInfo &TII); 605 606 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 607 unsigned FrameReg, int &Offset, 608 const ARMBaseInstrInfo &TII, 609 const TargetRegisterInfo *TRI); 610 611 /// Return true if Reg is defd between From and To 612 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, 613 MachineBasicBlock::iterator To, 614 const TargetRegisterInfo *TRI); 615 616 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning 617 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found. 618 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, 619 const TargetRegisterInfo *TRI); 620 621 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); 622 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg); 623 624 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); 625 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, 626 unsigned Inactive); 627 628 /// Returns the number of instructions required to materialize the given 629 /// constant in a register, or 3 if a literal pool load is needed. 630 /// If ForCodesize is specified, an approximate cost in bytes is returned. 631 unsigned ConstantMaterializationCost(unsigned Val, 632 const ARMSubtarget *Subtarget, 633 bool ForCodesize = false); 634 635 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2. 636 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as 637 /// specified. If the scores are equal, return the comparison for !ForCodesize. 638 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, 639 const ARMSubtarget *Subtarget, 640 bool ForCodesize = false); 641 642 } // end namespace llvm 643 644 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 645