xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583) 
1*0fca6ea1SDimitry Andric //===--- AMDHSAKernelDescriptor.h -----------------------------------------===//
2*0fca6ea1SDimitry Andric //
3*0fca6ea1SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0fca6ea1SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0fca6ea1SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0fca6ea1SDimitry Andric //
7*0fca6ea1SDimitry Andric //===----------------------------------------------------------------------===//
8*0fca6ea1SDimitry Andric 
9*0fca6ea1SDimitry Andric #include "AMDGPUMCKernelDescriptor.h"
10*0fca6ea1SDimitry Andric #include "AMDGPUMCTargetDesc.h"
11*0fca6ea1SDimitry Andric #include "Utils/AMDGPUBaseInfo.h"
12*0fca6ea1SDimitry Andric #include "llvm/MC/MCContext.h"
13*0fca6ea1SDimitry Andric #include "llvm/MC/MCExpr.h"
14*0fca6ea1SDimitry Andric #include "llvm/MC/MCSubtargetInfo.h"
15*0fca6ea1SDimitry Andric #include "llvm/TargetParser/TargetParser.h"
16*0fca6ea1SDimitry Andric 
17*0fca6ea1SDimitry Andric using namespace llvm;
18*0fca6ea1SDimitry Andric using namespace llvm::AMDGPU;
19*0fca6ea1SDimitry Andric 
20*0fca6ea1SDimitry Andric MCKernelDescriptor
21*0fca6ea1SDimitry Andric MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI,
22*0fca6ea1SDimitry Andric                                                      MCContext &Ctx) {
23*0fca6ea1SDimitry Andric   IsaVersion Version = getIsaVersion(STI->getCPU());
24*0fca6ea1SDimitry Andric 
25*0fca6ea1SDimitry Andric   MCKernelDescriptor KD;
26*0fca6ea1SDimitry Andric   const MCExpr *ZeroMCExpr = MCConstantExpr::create(0, Ctx);
27*0fca6ea1SDimitry Andric   const MCExpr *OneMCExpr = MCConstantExpr::create(1, Ctx);
28*0fca6ea1SDimitry Andric 
29*0fca6ea1SDimitry Andric   KD.group_segment_fixed_size = ZeroMCExpr;
30*0fca6ea1SDimitry Andric   KD.private_segment_fixed_size = ZeroMCExpr;
31*0fca6ea1SDimitry Andric   KD.compute_pgm_rsrc1 = ZeroMCExpr;
32*0fca6ea1SDimitry Andric   KD.compute_pgm_rsrc2 = ZeroMCExpr;
33*0fca6ea1SDimitry Andric   KD.compute_pgm_rsrc3 = ZeroMCExpr;
34*0fca6ea1SDimitry Andric   KD.kernarg_size = ZeroMCExpr;
35*0fca6ea1SDimitry Andric   KD.kernel_code_properties = ZeroMCExpr;
36*0fca6ea1SDimitry Andric   KD.kernarg_preload = ZeroMCExpr;
37*0fca6ea1SDimitry Andric 
38*0fca6ea1SDimitry Andric   MCKernelDescriptor::bits_set(
39*0fca6ea1SDimitry Andric       KD.compute_pgm_rsrc1,
40*0fca6ea1SDimitry Andric       MCConstantExpr::create(amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, Ctx),
41*0fca6ea1SDimitry Andric       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
42*0fca6ea1SDimitry Andric       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Ctx);
43*0fca6ea1SDimitry Andric   if (Version.Major < 12) {
44*0fca6ea1SDimitry Andric     MCKernelDescriptor::bits_set(
45*0fca6ea1SDimitry Andric         KD.compute_pgm_rsrc1, OneMCExpr,
46*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
47*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Ctx);
48*0fca6ea1SDimitry Andric     MCKernelDescriptor::bits_set(
49*0fca6ea1SDimitry Andric         KD.compute_pgm_rsrc1, OneMCExpr,
50*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
51*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Ctx);
52*0fca6ea1SDimitry Andric   }
53*0fca6ea1SDimitry Andric   MCKernelDescriptor::bits_set(
54*0fca6ea1SDimitry Andric       KD.compute_pgm_rsrc2, OneMCExpr,
55*0fca6ea1SDimitry Andric       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
56*0fca6ea1SDimitry Andric       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx);
57*0fca6ea1SDimitry Andric   if (Version.Major >= 10) {
58*0fca6ea1SDimitry Andric     if (STI->getFeatureBits().test(FeatureWavefrontSize32))
59*0fca6ea1SDimitry Andric       MCKernelDescriptor::bits_set(
60*0fca6ea1SDimitry Andric           KD.kernel_code_properties, OneMCExpr,
61*0fca6ea1SDimitry Andric           amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
62*0fca6ea1SDimitry Andric           amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx);
63*0fca6ea1SDimitry Andric     if (!STI->getFeatureBits().test(FeatureCuMode))
64*0fca6ea1SDimitry Andric       MCKernelDescriptor::bits_set(
65*0fca6ea1SDimitry Andric           KD.compute_pgm_rsrc1, OneMCExpr,
66*0fca6ea1SDimitry Andric           amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
67*0fca6ea1SDimitry Andric           amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Ctx);
68*0fca6ea1SDimitry Andric 
69*0fca6ea1SDimitry Andric     MCKernelDescriptor::bits_set(
70*0fca6ea1SDimitry Andric         KD.compute_pgm_rsrc1, OneMCExpr,
71*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
72*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Ctx);
73*0fca6ea1SDimitry Andric   }
74*0fca6ea1SDimitry Andric   if (AMDGPU::isGFX90A(*STI) && STI->getFeatureBits().test(FeatureTgSplit))
75*0fca6ea1SDimitry Andric     MCKernelDescriptor::bits_set(
76*0fca6ea1SDimitry Andric         KD.compute_pgm_rsrc3, OneMCExpr,
77*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
78*0fca6ea1SDimitry Andric         amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx);
79*0fca6ea1SDimitry Andric   return KD;
80*0fca6ea1SDimitry Andric }
81*0fca6ea1SDimitry Andric 
82*0fca6ea1SDimitry Andric void MCKernelDescriptor::bits_set(const MCExpr *&Dst, const MCExpr *Value,
83*0fca6ea1SDimitry Andric                                   uint32_t Shift, uint32_t Mask,
84*0fca6ea1SDimitry Andric                                   MCContext &Ctx) {
85*0fca6ea1SDimitry Andric   auto Sft = MCConstantExpr::create(Shift, Ctx);
86*0fca6ea1SDimitry Andric   auto Msk = MCConstantExpr::create(Mask, Ctx);
87*0fca6ea1SDimitry Andric   Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx);
88*0fca6ea1SDimitry Andric   Dst = MCBinaryExpr::createOr(Dst, MCBinaryExpr::createShl(Value, Sft, Ctx),
89*0fca6ea1SDimitry Andric                                Ctx);
90*0fca6ea1SDimitry Andric }
91*0fca6ea1SDimitry Andric 
92*0fca6ea1SDimitry Andric const MCExpr *MCKernelDescriptor::bits_get(const MCExpr *Src, uint32_t Shift,
93*0fca6ea1SDimitry Andric                                            uint32_t Mask, MCContext &Ctx) {
94*0fca6ea1SDimitry Andric   auto Sft = MCConstantExpr::create(Shift, Ctx);
95*0fca6ea1SDimitry Andric   auto Msk = MCConstantExpr::create(Mask, Ctx);
96*0fca6ea1SDimitry Andric   return MCBinaryExpr::createLShr(MCBinaryExpr::createAnd(Src, Msk, Ctx), Sft,
97*0fca6ea1SDimitry Andric                                   Ctx);
98*0fca6ea1SDimitry Andric }
99