1*753f127fSDimitry Andric //===- GCNVOPDUtils.h - GCN VOPD Utils ------------------------===// 2*753f127fSDimitry Andric // 3*753f127fSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*753f127fSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*753f127fSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*753f127fSDimitry Andric // 7*753f127fSDimitry Andric //===----------------------------------------------------------------------===// 8*753f127fSDimitry Andric // 9*753f127fSDimitry Andric /// \file This file contains the AMDGPU DAG scheduling 10*753f127fSDimitry Andric /// mutation to pair VOPD instructions back to back. It also contains 11*753f127fSDimitry Andric // subroutines useful in the creation of VOPD instructions 12*753f127fSDimitry Andric // 13*753f127fSDimitry Andric //===----------------------------------------------------------------------===// 14*753f127fSDimitry Andric 15*753f127fSDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H 16*753f127fSDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H 17*753f127fSDimitry Andric 18*753f127fSDimitry Andric #include "llvm/CodeGen/MachineScheduler.h" 19*753f127fSDimitry Andric 20*753f127fSDimitry Andric namespace llvm { 21*753f127fSDimitry Andric 22*753f127fSDimitry Andric class SIInstrInfo; 23*753f127fSDimitry Andric 24*753f127fSDimitry Andric bool checkVOPDRegConstraints(const SIInstrInfo &TII, 25*753f127fSDimitry Andric const MachineInstr &FirstMI, 26*753f127fSDimitry Andric const MachineInstr &SecondMI); 27*753f127fSDimitry Andric 28*753f127fSDimitry Andric std::unique_ptr<ScheduleDAGMutation> createVOPDPairingMutation(); 29*753f127fSDimitry Andric 30*753f127fSDimitry Andric } // namespace llvm 31*753f127fSDimitry Andric 32*753f127fSDimitry Andric #endif // LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H 33