1*06c3fb27SDimitry Andric //===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==// 2*06c3fb27SDimitry Andric // 3*06c3fb27SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*06c3fb27SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*06c3fb27SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*06c3fb27SDimitry Andric // 7*06c3fb27SDimitry Andric //===----------------------------------------------------------------------===// 8*06c3fb27SDimitry Andric // 9*06c3fb27SDimitry Andric // Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR 10*06c3fb27SDimitry Andric // register bank selection. Use/def analysis as in the default RegBankSelect can 11*06c3fb27SDimitry Andric // be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908). 12*06c3fb27SDimitry Andric // 13*06c3fb27SDimitry Andric //===----------------------------------------------------------------------===// 14*06c3fb27SDimitry Andric 15*06c3fb27SDimitry Andric #include "AMDGPURegBankSelect.h" 16*06c3fb27SDimitry Andric #include "AMDGPU.h" 17*06c3fb27SDimitry Andric #include "GCNSubtarget.h" 18*06c3fb27SDimitry Andric #include "llvm/CodeGen/MachineUniformityAnalysis.h" 19*06c3fb27SDimitry Andric #include "llvm/InitializePasses.h" 20*06c3fb27SDimitry Andric 21*06c3fb27SDimitry Andric #define DEBUG_TYPE "regbankselect" 22*06c3fb27SDimitry Andric 23*06c3fb27SDimitry Andric using namespace llvm; 24*06c3fb27SDimitry Andric 25*06c3fb27SDimitry Andric AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode) 26*06c3fb27SDimitry Andric : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {} 27*06c3fb27SDimitry Andric 28*06c3fb27SDimitry Andric char AMDGPURegBankSelect::ID = 0; 29*06c3fb27SDimitry Andric 30*06c3fb27SDimitry Andric StringRef AMDGPURegBankSelect::getPassName() const { 31*06c3fb27SDimitry Andric return "AMDGPURegBankSelect"; 32*06c3fb27SDimitry Andric } 33*06c3fb27SDimitry Andric 34*06c3fb27SDimitry Andric void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const { 35*06c3fb27SDimitry Andric AU.addRequired<MachineCycleInfoWrapperPass>(); 36*06c3fb27SDimitry Andric AU.addRequired<MachineDominatorTree>(); 37*06c3fb27SDimitry Andric // TODO: Preserve DomTree 38*06c3fb27SDimitry Andric RegBankSelect::getAnalysisUsage(AU); 39*06c3fb27SDimitry Andric } 40*06c3fb27SDimitry Andric 41*06c3fb27SDimitry Andric INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, 42*06c3fb27SDimitry Andric "AMDGPU Register Bank Select", false, false) 43*06c3fb27SDimitry Andric INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 44*06c3fb27SDimitry Andric INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 45*06c3fb27SDimitry Andric INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, 46*06c3fb27SDimitry Andric "AMDGPU Register Bank Select", false, false) 47*06c3fb27SDimitry Andric 48*06c3fb27SDimitry Andric bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { 49*06c3fb27SDimitry Andric // If the ISel pipeline failed, do not bother running that pass. 50*06c3fb27SDimitry Andric if (MF.getProperties().hasProperty( 51*06c3fb27SDimitry Andric MachineFunctionProperties::Property::FailedISel)) 52*06c3fb27SDimitry Andric return false; 53*06c3fb27SDimitry Andric 54*06c3fb27SDimitry Andric LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); 55*06c3fb27SDimitry Andric const Function &F = MF.getFunction(); 56*06c3fb27SDimitry Andric Mode SaveOptMode = OptMode; 57*06c3fb27SDimitry Andric if (F.hasOptNone()) 58*06c3fb27SDimitry Andric OptMode = Mode::Fast; 59*06c3fb27SDimitry Andric init(MF); 60*06c3fb27SDimitry Andric 61*06c3fb27SDimitry Andric assert(checkFunctionIsLegal(MF)); 62*06c3fb27SDimitry Andric 63*06c3fb27SDimitry Andric const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 64*06c3fb27SDimitry Andric MachineCycleInfo &CycleInfo = 65*06c3fb27SDimitry Andric getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo(); 66*06c3fb27SDimitry Andric MachineDominatorTree &DomTree = getAnalysis<MachineDominatorTree>(); 67*06c3fb27SDimitry Andric 68*06c3fb27SDimitry Andric MachineUniformityInfo Uniformity = 69*06c3fb27SDimitry Andric computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(), 70*06c3fb27SDimitry Andric !ST.isSingleLaneExecution(F)); 71*06c3fb27SDimitry Andric (void)Uniformity; // TODO: Use this 72*06c3fb27SDimitry Andric 73*06c3fb27SDimitry Andric assignRegisterBanks(MF); 74*06c3fb27SDimitry Andric 75*06c3fb27SDimitry Andric OptMode = SaveOptMode; 76*06c3fb27SDimitry Andric return false; 77*06c3fb27SDimitry Andric } 78