106c3fb27SDimitry Andric //===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==// 206c3fb27SDimitry Andric // 306c3fb27SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406c3fb27SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 506c3fb27SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606c3fb27SDimitry Andric // 706c3fb27SDimitry Andric //===----------------------------------------------------------------------===// 806c3fb27SDimitry Andric // 906c3fb27SDimitry Andric // Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR 1006c3fb27SDimitry Andric // register bank selection. Use/def analysis as in the default RegBankSelect can 1106c3fb27SDimitry Andric // be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908). 1206c3fb27SDimitry Andric // 1306c3fb27SDimitry Andric //===----------------------------------------------------------------------===// 1406c3fb27SDimitry Andric 1506c3fb27SDimitry Andric #include "AMDGPURegBankSelect.h" 1606c3fb27SDimitry Andric #include "AMDGPU.h" 1706c3fb27SDimitry Andric #include "GCNSubtarget.h" 1806c3fb27SDimitry Andric #include "llvm/CodeGen/MachineUniformityAnalysis.h" 1906c3fb27SDimitry Andric #include "llvm/InitializePasses.h" 2006c3fb27SDimitry Andric 2106c3fb27SDimitry Andric #define DEBUG_TYPE "regbankselect" 2206c3fb27SDimitry Andric 2306c3fb27SDimitry Andric using namespace llvm; 2406c3fb27SDimitry Andric 2506c3fb27SDimitry Andric AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode) 2606c3fb27SDimitry Andric : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {} 2706c3fb27SDimitry Andric 2806c3fb27SDimitry Andric char AMDGPURegBankSelect::ID = 0; 2906c3fb27SDimitry Andric 3006c3fb27SDimitry Andric StringRef AMDGPURegBankSelect::getPassName() const { 3106c3fb27SDimitry Andric return "AMDGPURegBankSelect"; 3206c3fb27SDimitry Andric } 3306c3fb27SDimitry Andric 3406c3fb27SDimitry Andric void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const { 3506c3fb27SDimitry Andric AU.addRequired<MachineCycleInfoWrapperPass>(); 36*0fca6ea1SDimitry Andric AU.addRequired<MachineDominatorTreeWrapperPass>(); 3706c3fb27SDimitry Andric // TODO: Preserve DomTree 3806c3fb27SDimitry Andric RegBankSelect::getAnalysisUsage(AU); 3906c3fb27SDimitry Andric } 4006c3fb27SDimitry Andric 4106c3fb27SDimitry Andric INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, 4206c3fb27SDimitry Andric "AMDGPU Register Bank Select", false, false) 4306c3fb27SDimitry Andric INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 44*0fca6ea1SDimitry Andric INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) 4506c3fb27SDimitry Andric INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, 4606c3fb27SDimitry Andric "AMDGPU Register Bank Select", false, false) 4706c3fb27SDimitry Andric 4806c3fb27SDimitry Andric bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { 4906c3fb27SDimitry Andric // If the ISel pipeline failed, do not bother running that pass. 5006c3fb27SDimitry Andric if (MF.getProperties().hasProperty( 5106c3fb27SDimitry Andric MachineFunctionProperties::Property::FailedISel)) 5206c3fb27SDimitry Andric return false; 5306c3fb27SDimitry Andric 5406c3fb27SDimitry Andric LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); 5506c3fb27SDimitry Andric const Function &F = MF.getFunction(); 5606c3fb27SDimitry Andric Mode SaveOptMode = OptMode; 5706c3fb27SDimitry Andric if (F.hasOptNone()) 5806c3fb27SDimitry Andric OptMode = Mode::Fast; 5906c3fb27SDimitry Andric init(MF); 6006c3fb27SDimitry Andric 6106c3fb27SDimitry Andric assert(checkFunctionIsLegal(MF)); 6206c3fb27SDimitry Andric 6306c3fb27SDimitry Andric const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 6406c3fb27SDimitry Andric MachineCycleInfo &CycleInfo = 6506c3fb27SDimitry Andric getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo(); 66*0fca6ea1SDimitry Andric MachineDominatorTree &DomTree = 67*0fca6ea1SDimitry Andric getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); 6806c3fb27SDimitry Andric 6906c3fb27SDimitry Andric MachineUniformityInfo Uniformity = 7006c3fb27SDimitry Andric computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(), 7106c3fb27SDimitry Andric !ST.isSingleLaneExecution(F)); 7206c3fb27SDimitry Andric (void)Uniformity; // TODO: Use this 7306c3fb27SDimitry Andric 7406c3fb27SDimitry Andric assignRegisterBanks(MF); 7506c3fb27SDimitry Andric 7606c3fb27SDimitry Andric OptMode = SaveOptMode; 7706c3fb27SDimitry Andric return false; 7806c3fb27SDimitry Andric } 79