1480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric 9480093f4SDimitry Andric #include "AMDGPUGlobalISelUtils.h" 10480093f4SDimitry Andric #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 11480093f4SDimitry Andric #include "llvm/IR/Constants.h" 12480093f4SDimitry Andric 13480093f4SDimitry Andric using namespace llvm; 14480093f4SDimitry Andric using namespace MIPatternMatch; 15480093f4SDimitry Andric 16*e8d8bef9SDimitry Andric std::pair<Register, unsigned> 17480093f4SDimitry Andric AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) { 18480093f4SDimitry Andric MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); 19480093f4SDimitry Andric if (!Def) 20*e8d8bef9SDimitry Andric return std::make_pair(Reg, 0); 21480093f4SDimitry Andric 22480093f4SDimitry Andric if (Def->getOpcode() == TargetOpcode::G_CONSTANT) { 23480093f4SDimitry Andric unsigned Offset; 24480093f4SDimitry Andric const MachineOperand &Op = Def->getOperand(1); 25480093f4SDimitry Andric if (Op.isImm()) 26480093f4SDimitry Andric Offset = Op.getImm(); 27480093f4SDimitry Andric else 28480093f4SDimitry Andric Offset = Op.getCImm()->getZExtValue(); 29480093f4SDimitry Andric 30*e8d8bef9SDimitry Andric return std::make_pair(Register(), Offset); 31480093f4SDimitry Andric } 32480093f4SDimitry Andric 33480093f4SDimitry Andric int64_t Offset; 34480093f4SDimitry Andric if (Def->getOpcode() == TargetOpcode::G_ADD) { 35480093f4SDimitry Andric // TODO: Handle G_OR used for add case 36480093f4SDimitry Andric if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset))) 37*e8d8bef9SDimitry Andric return std::make_pair(Def->getOperand(1).getReg(), Offset); 38480093f4SDimitry Andric 39480093f4SDimitry Andric // FIXME: matcher should ignore copies 40480093f4SDimitry Andric if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset)))) 41*e8d8bef9SDimitry Andric return std::make_pair(Def->getOperand(1).getReg(), Offset); 42480093f4SDimitry Andric } 43480093f4SDimitry Andric 44*e8d8bef9SDimitry Andric return std::make_pair(Reg, 0); 45480093f4SDimitry Andric } 465ffd83dbSDimitry Andric 475ffd83dbSDimitry Andric bool AMDGPU::isLegalVOP3PShuffleMask(ArrayRef<int> Mask) { 485ffd83dbSDimitry Andric assert(Mask.size() == 2); 495ffd83dbSDimitry Andric 505ffd83dbSDimitry Andric // If one half is undef, the other is trivially in the same reg. 515ffd83dbSDimitry Andric if (Mask[0] == -1 || Mask[1] == -1) 525ffd83dbSDimitry Andric return true; 535ffd83dbSDimitry Andric return (Mask[0] & 2) == (Mask[1] & 2); 545ffd83dbSDimitry Andric } 55