1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDecoderOps.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrDesc.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/TargetRegistry.h" 26 #include "llvm/Support/Compiler.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include <algorithm> 30 #include <memory> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "aarch64-disassembler" 35 36 // Pull DecodeStatus and its enum values into the global namespace. 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 // Forward declare these because the autogenerated code will reference them. 40 // Definitions are further down. 41 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 42 uint64_t Address, 43 const MCDisassembler *Decoder); 44 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 45 uint64_t Address, 46 const MCDisassembler *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const MCDisassembler *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const MCDisassembler *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const MCDisassembler *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const MCDisassembler *Decoder); 59 static DecodeStatus 60 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 61 const MCDisassembler *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const MCDisassembler *Decoder); 65 static DecodeStatus 66 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 67 const MCDisassembler *Decoder); 68 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const MCDisassembler *Decoder); 71 static DecodeStatus 72 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, 74 const MCDisassembler *Decoder); 75 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 76 uint64_t Address, 77 const MCDisassembler *Decoder); 78 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const MCDisassembler *Decoder); 81 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const MCDisassembler *Decoder); 84 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const MCDisassembler *Decoder); 87 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const MCDisassembler *Decoder); 90 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const MCDisassembler *Decoder); 93 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const MCDisassembler *Decoder); 96 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const MCDisassembler *Decoder); 99 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const MCDisassembler *Decoder); 102 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const MCDisassembler *Decoder); 105 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const MCDisassembler *Decoder); 108 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const MCDisassembler *Decoder); 111 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const MCDisassembler *Decoder); 114 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const MCDisassembler *Decoder); 117 template <unsigned NumBitsForTile> 118 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const MCDisassembler *Decoder); 121 static DecodeStatus 122 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 123 uint64_t Address, 124 const MCDisassembler *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const MCDisassembler *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const MCDisassembler *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const MCDisassembler *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const MCDisassembler *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, 140 const MCDisassembler *Decoder); 141 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 142 uint64_t Address, 143 const MCDisassembler *Decoder); 144 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, 146 const MCDisassembler *Decoder); 147 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 148 uint64_t Address, 149 const MCDisassembler *Decoder); 150 static DecodeStatus 151 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 152 const MCDisassembler *Decoder); 153 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 154 uint64_t Address, 155 const MCDisassembler *Decoder); 156 static DecodeStatus 157 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 158 const MCDisassembler *Decoder); 159 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const MCDisassembler *Decoder); 162 static DecodeStatus 163 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 164 const MCDisassembler *Decoder); 165 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const MCDisassembler *Decoder); 168 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, 170 const MCDisassembler *Decoder); 171 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 172 uint64_t Address, 173 const MCDisassembler *Decoder); 174 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 175 uint64_t Address, 176 const MCDisassembler *Decoder); 177 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 178 uint64_t Address, 179 const MCDisassembler *Decoder); 180 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 181 uint64_t Address, 182 const MCDisassembler *Decoder); 183 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus 193 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 199 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 200 uint64_t Address, 201 const MCDisassembler *Decoder); 202 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const MCDisassembler *Decoder); 205 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder); 208 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, 210 const MCDisassembler *Decoder); 211 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 212 uint64_t Addr, 213 const MCDisassembler *Decoder); 214 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, 216 const MCDisassembler *Decoder); 217 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, 219 const MCDisassembler *Decoder); 220 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder); 223 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, 225 const MCDisassembler *Decoder); 226 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder); 229 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 230 uint64_t Addr, 231 const MCDisassembler *Decoder); 232 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 233 uint64_t Addr, 234 const MCDisassembler *Decoder); 235 static DecodeStatus 236 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 237 const MCDisassembler *Decoder); 238 static DecodeStatus 239 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 240 const MCDisassembler *Decoder); 241 static DecodeStatus 242 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 243 const MCDisassembler *Decoder); 244 template <int Bits> 245 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 246 const MCDisassembler *Decoder); 247 template <int ElementWidth> 248 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 249 const MCDisassembler *Decoder); 250 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 251 uint64_t Addr, 252 const MCDisassembler *Decoder); 253 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 256 uint64_t Addr, 257 const MCDisassembler *Decoder); 258 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 259 uint64_t Addr, 260 const MCDisassembler *Decoder); 261 262 static bool Check(DecodeStatus &Out, DecodeStatus In) { 263 switch (In) { 264 case MCDisassembler::Success: 265 // Out stays the same. 266 return true; 267 case MCDisassembler::SoftFail: 268 Out = In; 269 return true; 270 case MCDisassembler::Fail: 271 Out = In; 272 return false; 273 } 274 llvm_unreachable("Invalid DecodeStatus!"); 275 } 276 277 #include "AArch64GenDisassemblerTables.inc" 278 #include "AArch64GenInstrInfo.inc" 279 280 #define Success MCDisassembler::Success 281 #define Fail MCDisassembler::Fail 282 #define SoftFail MCDisassembler::SoftFail 283 284 static MCDisassembler *createAArch64Disassembler(const Target &T, 285 const MCSubtargetInfo &STI, 286 MCContext &Ctx) { 287 288 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo()); 289 } 290 291 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 292 ArrayRef<uint8_t> Bytes, 293 uint64_t Address, 294 raw_ostream &CS) const { 295 CommentStream = &CS; 296 297 Size = 0; 298 // We want to read exactly 4 bytes of data. 299 if (Bytes.size() < 4) 300 return Fail; 301 Size = 4; 302 303 // Encoded as a small-endian 32-bit word in the stream. 304 uint32_t Insn = 305 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 306 307 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 308 309 for (auto Table : Tables) { 310 DecodeStatus Result = 311 decodeInstruction(Table, MI, Insn, Address, this, STI); 312 313 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 314 315 // For Scalable Matrix Extension (SME) instructions that have an implicit 316 // operand for the accumulator (ZA) or implicit immediate zero which isn't 317 // encoded, manually insert operand. 318 for (unsigned i = 0; i < Desc.getNumOperands(); i++) { 319 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_REGISTER) { 320 switch (Desc.OpInfo[i].RegClass) { 321 default: 322 break; 323 case AArch64::MPRRegClassID: 324 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); 325 break; 326 case AArch64::MPR8RegClassID: 327 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); 328 break; 329 } 330 } else if (Desc.OpInfo[i].OperandType == 331 AArch64::OPERAND_IMPLICIT_IMM_0) { 332 MI.insert(MI.begin() + i, MCOperand::createImm(0)); 333 } 334 } 335 336 if (MI.getOpcode() == AArch64::LDR_ZA || 337 MI.getOpcode() == AArch64::STR_ZA) { 338 // Spill and fill instructions have a single immediate used for both 339 // the vector select offset and optional memory offset. Replicate 340 // the decoded immediate. 341 const MCOperand &Imm4Op = MI.getOperand(2); 342 assert(Imm4Op.isImm() && "Unexpected operand type!"); 343 MI.addOperand(Imm4Op); 344 } 345 346 if (Result != MCDisassembler::Fail) 347 return Result; 348 } 349 350 return MCDisassembler::Fail; 351 } 352 353 static MCSymbolizer * 354 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 355 LLVMSymbolLookupCallback SymbolLookUp, 356 void *DisInfo, MCContext *Ctx, 357 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 358 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 359 SymbolLookUp, DisInfo); 360 } 361 362 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 363 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 364 createAArch64Disassembler); 365 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 366 createAArch64Disassembler); 367 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 368 createAArch64ExternalSymbolizer); 369 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 370 createAArch64ExternalSymbolizer); 371 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 372 createAArch64Disassembler); 373 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 374 createAArch64ExternalSymbolizer); 375 376 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 377 createAArch64Disassembler); 378 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 379 createAArch64ExternalSymbolizer); 380 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 381 createAArch64Disassembler); 382 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 383 createAArch64ExternalSymbolizer); 384 } 385 386 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 387 uint64_t Addr, 388 const MCDisassembler *Decoder) { 389 if (RegNo > 31) 390 return Fail; 391 392 unsigned Register = 393 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 394 Inst.addOperand(MCOperand::createReg(Register)); 395 return Success; 396 } 397 398 static DecodeStatus 399 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 400 const MCDisassembler *Decoder) { 401 if (RegNo > 15) 402 return Fail; 403 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 404 } 405 406 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 407 uint64_t Addr, 408 const MCDisassembler *Decoder) { 409 if (RegNo > 31) 410 return Fail; 411 412 unsigned Register = 413 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 414 Inst.addOperand(MCOperand::createReg(Register)); 415 return Success; 416 } 417 418 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 419 uint64_t Addr, 420 const MCDisassembler *Decoder) { 421 if (RegNo > 31) 422 return Fail; 423 424 unsigned Register = 425 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 426 Inst.addOperand(MCOperand::createReg(Register)); 427 return Success; 428 } 429 430 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 431 uint64_t Addr, 432 const MCDisassembler *Decoder) { 433 if (RegNo > 31) 434 return Fail; 435 436 unsigned Register = 437 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 438 Inst.addOperand(MCOperand::createReg(Register)); 439 return Success; 440 } 441 442 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 443 uint64_t Addr, 444 const MCDisassembler *Decoder) { 445 if (RegNo > 31) 446 return Fail; 447 448 unsigned Register = 449 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 450 Inst.addOperand(MCOperand::createReg(Register)); 451 return Success; 452 } 453 454 static DecodeStatus 455 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 456 const MCDisassembler *Decoder) { 457 if (RegNo > 30) 458 return Fail; 459 460 unsigned Register = 461 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 462 RegNo); 463 Inst.addOperand(MCOperand::createReg(Register)); 464 return Success; 465 } 466 467 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 468 uint64_t Addr, 469 const MCDisassembler *Decoder) { 470 if (RegNo > 31) 471 return Fail; 472 473 unsigned Register = 474 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 475 Inst.addOperand(MCOperand::createReg(Register)); 476 return Success; 477 } 478 479 static DecodeStatus 480 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 481 const MCDisassembler *Decoder) { 482 if (RegNo > 22) 483 return Fail; 484 if (RegNo & 1) 485 return Fail; 486 487 unsigned Register = 488 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 489 RegNo >> 1); 490 Inst.addOperand(MCOperand::createReg(Register)); 491 return Success; 492 } 493 494 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 495 uint64_t Addr, 496 const MCDisassembler *Decoder) { 497 if (RegNo > 31) 498 return Fail; 499 unsigned Register = 500 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 501 Inst.addOperand(MCOperand::createReg(Register)); 502 return Success; 503 } 504 505 static DecodeStatus 506 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 507 uint64_t Addr, 508 const MCDisassembler *Decoder) { 509 if (RegNo > 3) 510 return Fail; 511 512 unsigned Register = 513 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 514 .getRegister(RegNo); 515 Inst.addOperand(MCOperand::createReg(Register)); 516 return Success; 517 } 518 519 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 520 uint64_t Addr, 521 const MCDisassembler *Decoder) { 522 if (RegNo > 31) 523 return Fail; 524 525 unsigned Register = 526 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 527 Inst.addOperand(MCOperand::createReg(Register)); 528 return Success; 529 } 530 531 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 532 uint64_t Addr, 533 const MCDisassembler *Decoder) { 534 if (RegNo > 31) 535 return Fail; 536 537 unsigned Register = 538 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 539 Inst.addOperand(MCOperand::createReg(Register)); 540 return Success; 541 } 542 543 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 544 uint64_t Address, 545 const MCDisassembler *Decoder) { 546 if (RegNo > 31) 547 return Fail; 548 549 unsigned Register = 550 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 551 Inst.addOperand(MCOperand::createReg(Register)); 552 return Success; 553 } 554 555 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 556 uint64_t Address, 557 const MCDisassembler *Decoder) { 558 if (RegNo > 15) 559 return Fail; 560 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 561 } 562 563 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t Address, 565 const MCDisassembler *Decoder) { 566 if (RegNo > 7) 567 return Fail; 568 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 569 } 570 571 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 572 uint64_t Address, 573 const MCDisassembler *Decoder) { 574 if (RegNo > 31) 575 return Fail; 576 unsigned Register = 577 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 578 Inst.addOperand(MCOperand::createReg(Register)); 579 return Success; 580 } 581 582 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 583 uint64_t Address, 584 const MCDisassembler *Decoder) { 585 if (RegNo > 31) 586 return Fail; 587 unsigned Register = 588 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 589 Inst.addOperand(MCOperand::createReg(Register)); 590 return Success; 591 } 592 593 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 594 uint64_t Address, 595 const MCDisassembler *Decoder) { 596 if (RegNo > 31) 597 return Fail; 598 unsigned Register = 599 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 600 Inst.addOperand(MCOperand::createReg(Register)); 601 return Success; 602 } 603 604 static DecodeStatus 605 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 606 uint64_t Address, 607 const MCDisassembler *Decoder) { 608 if (RegMask > 0xFF) 609 return Fail; 610 Inst.addOperand(MCOperand::createImm(RegMask)); 611 return Success; 612 } 613 614 static const SmallVector<SmallVector<unsigned, 16>, 5> 615 MatrixZATileDecoderTable = { 616 {AArch64::ZAB0}, 617 {AArch64::ZAH0, AArch64::ZAH1}, 618 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 619 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 620 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 621 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 622 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 623 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 624 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 625 626 template <unsigned NumBitsForTile> 627 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 628 uint64_t Address, 629 const MCDisassembler *Decoder) { 630 unsigned LastReg = (1 << NumBitsForTile) - 1; 631 if (RegNo > LastReg) 632 return Fail; 633 Inst.addOperand( 634 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 635 return Success; 636 } 637 638 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 639 uint64_t Addr, 640 const MCDisassembler *Decoder) { 641 if (RegNo > 15) 642 return Fail; 643 644 unsigned Register = 645 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 646 Inst.addOperand(MCOperand::createReg(Register)); 647 return Success; 648 } 649 650 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 651 uint64_t Addr, 652 const MCDisassembler *Decoder) { 653 if (RegNo > 7) 654 return Fail; 655 656 // Just reuse the PPR decode table 657 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 658 } 659 660 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 661 uint64_t Addr, 662 const MCDisassembler *Decoder) { 663 if (RegNo > 31) 664 return Fail; 665 unsigned Register = 666 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 667 Inst.addOperand(MCOperand::createReg(Register)); 668 return Success; 669 } 670 671 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 672 uint64_t Addr, 673 const MCDisassembler *Decoder) { 674 if (RegNo > 31) 675 return Fail; 676 unsigned Register = 677 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 678 Inst.addOperand(MCOperand::createReg(Register)); 679 return Success; 680 } 681 682 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 683 uint64_t Addr, 684 const MCDisassembler *Decoder) { 685 if (RegNo > 31) 686 return Fail; 687 unsigned Register = 688 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 689 Inst.addOperand(MCOperand::createReg(Register)); 690 return Success; 691 } 692 693 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 694 uint64_t Addr, 695 const MCDisassembler *Decoder) { 696 if (RegNo > 31) 697 return Fail; 698 unsigned Register = 699 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 700 Inst.addOperand(MCOperand::createReg(Register)); 701 return Success; 702 } 703 704 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 705 uint64_t Addr, 706 const MCDisassembler *Decoder) { 707 if (RegNo > 31) 708 return Fail; 709 unsigned Register = 710 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 711 Inst.addOperand(MCOperand::createReg(Register)); 712 return Success; 713 } 714 715 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 716 uint64_t Addr, 717 const MCDisassembler *Decoder) { 718 if (RegNo > 31) 719 return Fail; 720 unsigned Register = 721 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 722 Inst.addOperand(MCOperand::createReg(Register)); 723 return Success; 724 } 725 726 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 727 uint64_t Addr, 728 const MCDisassembler *Decoder) { 729 // scale{5} is asserted as 1 in tblgen. 730 Imm |= 0x20; 731 Inst.addOperand(MCOperand::createImm(64 - Imm)); 732 return Success; 733 } 734 735 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 736 uint64_t Addr, 737 const MCDisassembler *Decoder) { 738 Inst.addOperand(MCOperand::createImm(64 - Imm)); 739 return Success; 740 } 741 742 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 743 uint64_t Addr, 744 const MCDisassembler *Decoder) { 745 int64_t ImmVal = Imm; 746 747 // Sign-extend 19-bit immediate. 748 if (ImmVal & (1 << (19 - 1))) 749 ImmVal |= ~((1LL << 19) - 1); 750 751 if (!Decoder->tryAddingSymbolicOperand( 752 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) 753 Inst.addOperand(MCOperand::createImm(ImmVal)); 754 return Success; 755 } 756 757 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 758 uint64_t Address, 759 const MCDisassembler *Decoder) { 760 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 761 Inst.addOperand(MCOperand::createImm(Imm & 1)); 762 return Success; 763 } 764 765 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 766 uint64_t Address, 767 const MCDisassembler *Decoder) { 768 Inst.addOperand(MCOperand::createImm(Imm)); 769 770 // Every system register in the encoding space is valid with the syntax 771 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 772 return Success; 773 } 774 775 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 776 uint64_t Address, 777 const MCDisassembler *Decoder) { 778 Inst.addOperand(MCOperand::createImm(Imm)); 779 780 return Success; 781 } 782 783 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 784 uint64_t Address, 785 const MCDisassembler *Decoder) { 786 // This decoder exists to add the dummy Lane operand to the MCInst, which must 787 // be 1 in assembly but has no other real manifestation. 788 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 789 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 790 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 791 792 if (IsToVec) { 793 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 794 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 795 } else { 796 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 797 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 798 } 799 800 // Add the lane 801 Inst.addOperand(MCOperand::createImm(1)); 802 803 return Success; 804 } 805 806 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 807 unsigned Add) { 808 Inst.addOperand(MCOperand::createImm(Add - Imm)); 809 return Success; 810 } 811 812 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 813 unsigned Add) { 814 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 815 return Success; 816 } 817 818 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 819 uint64_t Addr, 820 const MCDisassembler *Decoder) { 821 return DecodeVecShiftRImm(Inst, Imm, 64); 822 } 823 824 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 825 uint64_t Addr, 826 const MCDisassembler *Decoder) { 827 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 828 } 829 830 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 831 uint64_t Addr, 832 const MCDisassembler *Decoder) { 833 return DecodeVecShiftRImm(Inst, Imm, 32); 834 } 835 836 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 837 uint64_t Addr, 838 const MCDisassembler *Decoder) { 839 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 840 } 841 842 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 843 uint64_t Addr, 844 const MCDisassembler *Decoder) { 845 return DecodeVecShiftRImm(Inst, Imm, 16); 846 } 847 848 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 849 uint64_t Addr, 850 const MCDisassembler *Decoder) { 851 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 852 } 853 854 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 855 uint64_t Addr, 856 const MCDisassembler *Decoder) { 857 return DecodeVecShiftRImm(Inst, Imm, 8); 858 } 859 860 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 861 uint64_t Addr, 862 const MCDisassembler *Decoder) { 863 return DecodeVecShiftLImm(Inst, Imm, 64); 864 } 865 866 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 867 uint64_t Addr, 868 const MCDisassembler *Decoder) { 869 return DecodeVecShiftLImm(Inst, Imm, 32); 870 } 871 872 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 873 uint64_t Addr, 874 const MCDisassembler *Decoder) { 875 return DecodeVecShiftLImm(Inst, Imm, 16); 876 } 877 878 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 879 uint64_t Addr, 880 const MCDisassembler *Decoder) { 881 return DecodeVecShiftLImm(Inst, Imm, 8); 882 } 883 884 static DecodeStatus 885 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 886 const MCDisassembler *Decoder) { 887 unsigned Rd = fieldFromInstruction(insn, 0, 5); 888 unsigned Rn = fieldFromInstruction(insn, 5, 5); 889 unsigned Rm = fieldFromInstruction(insn, 16, 5); 890 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 891 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 892 unsigned shift = (shiftHi << 6) | shiftLo; 893 switch (Inst.getOpcode()) { 894 default: 895 return Fail; 896 case AArch64::ADDWrs: 897 case AArch64::ADDSWrs: 898 case AArch64::SUBWrs: 899 case AArch64::SUBSWrs: 900 // if shift == '11' then ReservedValue() 901 if (shiftHi == 0x3) 902 return Fail; 903 LLVM_FALLTHROUGH; 904 case AArch64::ANDWrs: 905 case AArch64::ANDSWrs: 906 case AArch64::BICWrs: 907 case AArch64::BICSWrs: 908 case AArch64::ORRWrs: 909 case AArch64::ORNWrs: 910 case AArch64::EORWrs: 911 case AArch64::EONWrs: { 912 // if sf == '0' and imm6<5> == '1' then ReservedValue() 913 if (shiftLo >> 5 == 1) 914 return Fail; 915 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 916 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 917 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 918 break; 919 } 920 case AArch64::ADDXrs: 921 case AArch64::ADDSXrs: 922 case AArch64::SUBXrs: 923 case AArch64::SUBSXrs: 924 // if shift == '11' then ReservedValue() 925 if (shiftHi == 0x3) 926 return Fail; 927 LLVM_FALLTHROUGH; 928 case AArch64::ANDXrs: 929 case AArch64::ANDSXrs: 930 case AArch64::BICXrs: 931 case AArch64::BICSXrs: 932 case AArch64::ORRXrs: 933 case AArch64::ORNXrs: 934 case AArch64::EORXrs: 935 case AArch64::EONXrs: 936 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 937 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 938 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 939 break; 940 } 941 942 Inst.addOperand(MCOperand::createImm(shift)); 943 return Success; 944 } 945 946 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 947 uint64_t Addr, 948 const MCDisassembler *Decoder) { 949 unsigned Rd = fieldFromInstruction(insn, 0, 5); 950 unsigned imm = fieldFromInstruction(insn, 5, 16); 951 unsigned shift = fieldFromInstruction(insn, 21, 2); 952 shift <<= 4; 953 switch (Inst.getOpcode()) { 954 default: 955 return Fail; 956 case AArch64::MOVZWi: 957 case AArch64::MOVNWi: 958 case AArch64::MOVKWi: 959 if (shift & (1U << 5)) 960 return Fail; 961 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 962 break; 963 case AArch64::MOVZXi: 964 case AArch64::MOVNXi: 965 case AArch64::MOVKXi: 966 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 967 break; 968 } 969 970 if (Inst.getOpcode() == AArch64::MOVKWi || 971 Inst.getOpcode() == AArch64::MOVKXi) 972 Inst.addOperand(Inst.getOperand(0)); 973 974 Inst.addOperand(MCOperand::createImm(imm)); 975 Inst.addOperand(MCOperand::createImm(shift)); 976 return Success; 977 } 978 979 static DecodeStatus 980 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 981 const MCDisassembler *Decoder) { 982 unsigned Rt = fieldFromInstruction(insn, 0, 5); 983 unsigned Rn = fieldFromInstruction(insn, 5, 5); 984 unsigned offset = fieldFromInstruction(insn, 10, 12); 985 986 switch (Inst.getOpcode()) { 987 default: 988 return Fail; 989 case AArch64::PRFMui: 990 // Rt is an immediate in prefetch. 991 Inst.addOperand(MCOperand::createImm(Rt)); 992 break; 993 case AArch64::STRBBui: 994 case AArch64::LDRBBui: 995 case AArch64::LDRSBWui: 996 case AArch64::STRHHui: 997 case AArch64::LDRHHui: 998 case AArch64::LDRSHWui: 999 case AArch64::STRWui: 1000 case AArch64::LDRWui: 1001 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1002 break; 1003 case AArch64::LDRSBXui: 1004 case AArch64::LDRSHXui: 1005 case AArch64::LDRSWui: 1006 case AArch64::STRXui: 1007 case AArch64::LDRXui: 1008 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1009 break; 1010 case AArch64::LDRQui: 1011 case AArch64::STRQui: 1012 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1013 break; 1014 case AArch64::LDRDui: 1015 case AArch64::STRDui: 1016 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1017 break; 1018 case AArch64::LDRSui: 1019 case AArch64::STRSui: 1020 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1021 break; 1022 case AArch64::LDRHui: 1023 case AArch64::STRHui: 1024 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1025 break; 1026 case AArch64::LDRBui: 1027 case AArch64::STRBui: 1028 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1029 break; 1030 } 1031 1032 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1033 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4)) 1034 Inst.addOperand(MCOperand::createImm(offset)); 1035 return Success; 1036 } 1037 1038 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1039 uint64_t Addr, 1040 const MCDisassembler *Decoder) { 1041 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1042 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1043 int64_t offset = fieldFromInstruction(insn, 12, 9); 1044 1045 // offset is a 9-bit signed immediate, so sign extend it to 1046 // fill the unsigned. 1047 if (offset & (1 << (9 - 1))) 1048 offset |= ~((1LL << 9) - 1); 1049 1050 // First operand is always the writeback to the address register, if needed. 1051 switch (Inst.getOpcode()) { 1052 default: 1053 break; 1054 case AArch64::LDRSBWpre: 1055 case AArch64::LDRSHWpre: 1056 case AArch64::STRBBpre: 1057 case AArch64::LDRBBpre: 1058 case AArch64::STRHHpre: 1059 case AArch64::LDRHHpre: 1060 case AArch64::STRWpre: 1061 case AArch64::LDRWpre: 1062 case AArch64::LDRSBWpost: 1063 case AArch64::LDRSHWpost: 1064 case AArch64::STRBBpost: 1065 case AArch64::LDRBBpost: 1066 case AArch64::STRHHpost: 1067 case AArch64::LDRHHpost: 1068 case AArch64::STRWpost: 1069 case AArch64::LDRWpost: 1070 case AArch64::LDRSBXpre: 1071 case AArch64::LDRSHXpre: 1072 case AArch64::STRXpre: 1073 case AArch64::LDRSWpre: 1074 case AArch64::LDRXpre: 1075 case AArch64::LDRSBXpost: 1076 case AArch64::LDRSHXpost: 1077 case AArch64::STRXpost: 1078 case AArch64::LDRSWpost: 1079 case AArch64::LDRXpost: 1080 case AArch64::LDRQpre: 1081 case AArch64::STRQpre: 1082 case AArch64::LDRQpost: 1083 case AArch64::STRQpost: 1084 case AArch64::LDRDpre: 1085 case AArch64::STRDpre: 1086 case AArch64::LDRDpost: 1087 case AArch64::STRDpost: 1088 case AArch64::LDRSpre: 1089 case AArch64::STRSpre: 1090 case AArch64::LDRSpost: 1091 case AArch64::STRSpost: 1092 case AArch64::LDRHpre: 1093 case AArch64::STRHpre: 1094 case AArch64::LDRHpost: 1095 case AArch64::STRHpost: 1096 case AArch64::LDRBpre: 1097 case AArch64::STRBpre: 1098 case AArch64::LDRBpost: 1099 case AArch64::STRBpost: 1100 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1101 break; 1102 } 1103 1104 switch (Inst.getOpcode()) { 1105 default: 1106 return Fail; 1107 case AArch64::PRFUMi: 1108 // Rt is an immediate in prefetch. 1109 Inst.addOperand(MCOperand::createImm(Rt)); 1110 break; 1111 case AArch64::STURBBi: 1112 case AArch64::LDURBBi: 1113 case AArch64::LDURSBWi: 1114 case AArch64::STURHHi: 1115 case AArch64::LDURHHi: 1116 case AArch64::LDURSHWi: 1117 case AArch64::STURWi: 1118 case AArch64::LDURWi: 1119 case AArch64::LDTRSBWi: 1120 case AArch64::LDTRSHWi: 1121 case AArch64::STTRWi: 1122 case AArch64::LDTRWi: 1123 case AArch64::STTRHi: 1124 case AArch64::LDTRHi: 1125 case AArch64::LDTRBi: 1126 case AArch64::STTRBi: 1127 case AArch64::LDRSBWpre: 1128 case AArch64::LDRSHWpre: 1129 case AArch64::STRBBpre: 1130 case AArch64::LDRBBpre: 1131 case AArch64::STRHHpre: 1132 case AArch64::LDRHHpre: 1133 case AArch64::STRWpre: 1134 case AArch64::LDRWpre: 1135 case AArch64::LDRSBWpost: 1136 case AArch64::LDRSHWpost: 1137 case AArch64::STRBBpost: 1138 case AArch64::LDRBBpost: 1139 case AArch64::STRHHpost: 1140 case AArch64::LDRHHpost: 1141 case AArch64::STRWpost: 1142 case AArch64::LDRWpost: 1143 case AArch64::STLURBi: 1144 case AArch64::STLURHi: 1145 case AArch64::STLURWi: 1146 case AArch64::LDAPURBi: 1147 case AArch64::LDAPURSBWi: 1148 case AArch64::LDAPURHi: 1149 case AArch64::LDAPURSHWi: 1150 case AArch64::LDAPURi: 1151 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1152 break; 1153 case AArch64::LDURSBXi: 1154 case AArch64::LDURSHXi: 1155 case AArch64::LDURSWi: 1156 case AArch64::STURXi: 1157 case AArch64::LDURXi: 1158 case AArch64::LDTRSBXi: 1159 case AArch64::LDTRSHXi: 1160 case AArch64::LDTRSWi: 1161 case AArch64::STTRXi: 1162 case AArch64::LDTRXi: 1163 case AArch64::LDRSBXpre: 1164 case AArch64::LDRSHXpre: 1165 case AArch64::STRXpre: 1166 case AArch64::LDRSWpre: 1167 case AArch64::LDRXpre: 1168 case AArch64::LDRSBXpost: 1169 case AArch64::LDRSHXpost: 1170 case AArch64::STRXpost: 1171 case AArch64::LDRSWpost: 1172 case AArch64::LDRXpost: 1173 case AArch64::LDAPURSWi: 1174 case AArch64::LDAPURSHXi: 1175 case AArch64::LDAPURSBXi: 1176 case AArch64::STLURXi: 1177 case AArch64::LDAPURXi: 1178 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1179 break; 1180 case AArch64::LDURQi: 1181 case AArch64::STURQi: 1182 case AArch64::LDRQpre: 1183 case AArch64::STRQpre: 1184 case AArch64::LDRQpost: 1185 case AArch64::STRQpost: 1186 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1187 break; 1188 case AArch64::LDURDi: 1189 case AArch64::STURDi: 1190 case AArch64::LDRDpre: 1191 case AArch64::STRDpre: 1192 case AArch64::LDRDpost: 1193 case AArch64::STRDpost: 1194 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1195 break; 1196 case AArch64::LDURSi: 1197 case AArch64::STURSi: 1198 case AArch64::LDRSpre: 1199 case AArch64::STRSpre: 1200 case AArch64::LDRSpost: 1201 case AArch64::STRSpost: 1202 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1203 break; 1204 case AArch64::LDURHi: 1205 case AArch64::STURHi: 1206 case AArch64::LDRHpre: 1207 case AArch64::STRHpre: 1208 case AArch64::LDRHpost: 1209 case AArch64::STRHpost: 1210 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1211 break; 1212 case AArch64::LDURBi: 1213 case AArch64::STURBi: 1214 case AArch64::LDRBpre: 1215 case AArch64::STRBpre: 1216 case AArch64::LDRBpost: 1217 case AArch64::STRBpost: 1218 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1219 break; 1220 } 1221 1222 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1223 Inst.addOperand(MCOperand::createImm(offset)); 1224 1225 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1226 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1227 bool IsFP = fieldFromInstruction(insn, 26, 1); 1228 1229 // Cannot write back to a transfer register (but xzr != sp). 1230 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1231 return SoftFail; 1232 1233 return Success; 1234 } 1235 1236 static DecodeStatus 1237 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1238 const MCDisassembler *Decoder) { 1239 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1240 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1241 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1242 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1243 1244 unsigned Opcode = Inst.getOpcode(); 1245 switch (Opcode) { 1246 default: 1247 return Fail; 1248 case AArch64::STLXRW: 1249 case AArch64::STLXRB: 1250 case AArch64::STLXRH: 1251 case AArch64::STXRW: 1252 case AArch64::STXRB: 1253 case AArch64::STXRH: 1254 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1255 LLVM_FALLTHROUGH; 1256 case AArch64::LDARW: 1257 case AArch64::LDARB: 1258 case AArch64::LDARH: 1259 case AArch64::LDAXRW: 1260 case AArch64::LDAXRB: 1261 case AArch64::LDAXRH: 1262 case AArch64::LDXRW: 1263 case AArch64::LDXRB: 1264 case AArch64::LDXRH: 1265 case AArch64::STLRW: 1266 case AArch64::STLRB: 1267 case AArch64::STLRH: 1268 case AArch64::STLLRW: 1269 case AArch64::STLLRB: 1270 case AArch64::STLLRH: 1271 case AArch64::LDLARW: 1272 case AArch64::LDLARB: 1273 case AArch64::LDLARH: 1274 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1275 break; 1276 case AArch64::STLXRX: 1277 case AArch64::STXRX: 1278 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1279 LLVM_FALLTHROUGH; 1280 case AArch64::LDARX: 1281 case AArch64::LDAXRX: 1282 case AArch64::LDXRX: 1283 case AArch64::STLRX: 1284 case AArch64::LDLARX: 1285 case AArch64::STLLRX: 1286 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1287 break; 1288 case AArch64::STLXPW: 1289 case AArch64::STXPW: 1290 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1291 LLVM_FALLTHROUGH; 1292 case AArch64::LDAXPW: 1293 case AArch64::LDXPW: 1294 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1295 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1296 break; 1297 case AArch64::STLXPX: 1298 case AArch64::STXPX: 1299 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1300 LLVM_FALLTHROUGH; 1301 case AArch64::LDAXPX: 1302 case AArch64::LDXPX: 1303 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1304 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1305 break; 1306 } 1307 1308 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1309 1310 // You shouldn't load to the same register twice in an instruction... 1311 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1312 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1313 Rt == Rt2) 1314 return SoftFail; 1315 1316 return Success; 1317 } 1318 1319 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1320 uint64_t Addr, 1321 const MCDisassembler *Decoder) { 1322 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1323 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1324 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1325 int64_t offset = fieldFromInstruction(insn, 15, 7); 1326 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1327 1328 // offset is a 7-bit signed immediate, so sign extend it to 1329 // fill the unsigned. 1330 if (offset & (1 << (7 - 1))) 1331 offset |= ~((1LL << 7) - 1); 1332 1333 unsigned Opcode = Inst.getOpcode(); 1334 bool NeedsDisjointWritebackTransfer = false; 1335 1336 // First operand is always writeback of base register. 1337 switch (Opcode) { 1338 default: 1339 break; 1340 case AArch64::LDPXpost: 1341 case AArch64::STPXpost: 1342 case AArch64::LDPSWpost: 1343 case AArch64::LDPXpre: 1344 case AArch64::STPXpre: 1345 case AArch64::LDPSWpre: 1346 case AArch64::LDPWpost: 1347 case AArch64::STPWpost: 1348 case AArch64::LDPWpre: 1349 case AArch64::STPWpre: 1350 case AArch64::LDPQpost: 1351 case AArch64::STPQpost: 1352 case AArch64::LDPQpre: 1353 case AArch64::STPQpre: 1354 case AArch64::LDPDpost: 1355 case AArch64::STPDpost: 1356 case AArch64::LDPDpre: 1357 case AArch64::STPDpre: 1358 case AArch64::LDPSpost: 1359 case AArch64::STPSpost: 1360 case AArch64::LDPSpre: 1361 case AArch64::STPSpre: 1362 case AArch64::STGPpre: 1363 case AArch64::STGPpost: 1364 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1365 break; 1366 } 1367 1368 switch (Opcode) { 1369 default: 1370 return Fail; 1371 case AArch64::LDPXpost: 1372 case AArch64::STPXpost: 1373 case AArch64::LDPSWpost: 1374 case AArch64::LDPXpre: 1375 case AArch64::STPXpre: 1376 case AArch64::LDPSWpre: 1377 case AArch64::STGPpre: 1378 case AArch64::STGPpost: 1379 NeedsDisjointWritebackTransfer = true; 1380 LLVM_FALLTHROUGH; 1381 case AArch64::LDNPXi: 1382 case AArch64::STNPXi: 1383 case AArch64::LDPXi: 1384 case AArch64::STPXi: 1385 case AArch64::LDPSWi: 1386 case AArch64::STGPi: 1387 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1388 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1389 break; 1390 case AArch64::LDPWpost: 1391 case AArch64::STPWpost: 1392 case AArch64::LDPWpre: 1393 case AArch64::STPWpre: 1394 NeedsDisjointWritebackTransfer = true; 1395 LLVM_FALLTHROUGH; 1396 case AArch64::LDNPWi: 1397 case AArch64::STNPWi: 1398 case AArch64::LDPWi: 1399 case AArch64::STPWi: 1400 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1401 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1402 break; 1403 case AArch64::LDNPQi: 1404 case AArch64::STNPQi: 1405 case AArch64::LDPQpost: 1406 case AArch64::STPQpost: 1407 case AArch64::LDPQi: 1408 case AArch64::STPQi: 1409 case AArch64::LDPQpre: 1410 case AArch64::STPQpre: 1411 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1412 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1413 break; 1414 case AArch64::LDNPDi: 1415 case AArch64::STNPDi: 1416 case AArch64::LDPDpost: 1417 case AArch64::STPDpost: 1418 case AArch64::LDPDi: 1419 case AArch64::STPDi: 1420 case AArch64::LDPDpre: 1421 case AArch64::STPDpre: 1422 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1423 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1424 break; 1425 case AArch64::LDNPSi: 1426 case AArch64::STNPSi: 1427 case AArch64::LDPSpost: 1428 case AArch64::STPSpost: 1429 case AArch64::LDPSi: 1430 case AArch64::STPSi: 1431 case AArch64::LDPSpre: 1432 case AArch64::STPSpre: 1433 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1434 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1435 break; 1436 } 1437 1438 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1439 Inst.addOperand(MCOperand::createImm(offset)); 1440 1441 // You shouldn't load to the same register twice in an instruction... 1442 if (IsLoad && Rt == Rt2) 1443 return SoftFail; 1444 1445 // ... or do any operation that writes-back to a transfer register. But note 1446 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1447 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1448 return SoftFail; 1449 1450 return Success; 1451 } 1452 1453 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1454 uint64_t Addr, 1455 const MCDisassembler *Decoder) { 1456 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1457 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1458 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1459 fieldFromInstruction(insn, 12, 9); 1460 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1461 1462 switch (Inst.getOpcode()) { 1463 default: 1464 return Fail; 1465 case AArch64::LDRAAwriteback: 1466 case AArch64::LDRABwriteback: 1467 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1468 Decoder); 1469 break; 1470 case AArch64::LDRAAindexed: 1471 case AArch64::LDRABindexed: 1472 break; 1473 } 1474 1475 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1476 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1477 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1478 1479 if (writeback && Rt == Rn && Rn != 31) { 1480 return SoftFail; 1481 } 1482 1483 return Success; 1484 } 1485 1486 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1487 uint64_t Addr, 1488 const MCDisassembler *Decoder) { 1489 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1490 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1491 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1492 unsigned extend = fieldFromInstruction(insn, 10, 6); 1493 1494 unsigned shift = extend & 0x7; 1495 if (shift > 4) 1496 return Fail; 1497 1498 switch (Inst.getOpcode()) { 1499 default: 1500 return Fail; 1501 case AArch64::ADDWrx: 1502 case AArch64::SUBWrx: 1503 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1504 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1505 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1506 break; 1507 case AArch64::ADDSWrx: 1508 case AArch64::SUBSWrx: 1509 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1510 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1511 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1512 break; 1513 case AArch64::ADDXrx: 1514 case AArch64::SUBXrx: 1515 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1516 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1517 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1518 break; 1519 case AArch64::ADDSXrx: 1520 case AArch64::SUBSXrx: 1521 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1522 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1523 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1524 break; 1525 case AArch64::ADDXrx64: 1526 case AArch64::SUBXrx64: 1527 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1528 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1529 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1530 break; 1531 case AArch64::SUBSXrx64: 1532 case AArch64::ADDSXrx64: 1533 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1534 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1535 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1536 break; 1537 } 1538 1539 Inst.addOperand(MCOperand::createImm(extend)); 1540 return Success; 1541 } 1542 1543 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1544 uint64_t Addr, 1545 const MCDisassembler *Decoder) { 1546 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1547 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1548 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1549 unsigned imm; 1550 1551 if (Datasize) { 1552 if (Inst.getOpcode() == AArch64::ANDSXri) 1553 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1554 else 1555 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1556 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1557 imm = fieldFromInstruction(insn, 10, 13); 1558 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1559 return Fail; 1560 } else { 1561 if (Inst.getOpcode() == AArch64::ANDSWri) 1562 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1563 else 1564 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1565 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1566 imm = fieldFromInstruction(insn, 10, 12); 1567 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1568 return Fail; 1569 } 1570 Inst.addOperand(MCOperand::createImm(imm)); 1571 return Success; 1572 } 1573 1574 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1575 uint64_t Addr, 1576 const MCDisassembler *Decoder) { 1577 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1578 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1579 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1580 imm |= fieldFromInstruction(insn, 5, 5); 1581 1582 if (Inst.getOpcode() == AArch64::MOVID) 1583 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1584 else 1585 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1586 1587 Inst.addOperand(MCOperand::createImm(imm)); 1588 1589 switch (Inst.getOpcode()) { 1590 default: 1591 break; 1592 case AArch64::MOVIv4i16: 1593 case AArch64::MOVIv8i16: 1594 case AArch64::MVNIv4i16: 1595 case AArch64::MVNIv8i16: 1596 case AArch64::MOVIv2i32: 1597 case AArch64::MOVIv4i32: 1598 case AArch64::MVNIv2i32: 1599 case AArch64::MVNIv4i32: 1600 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1601 break; 1602 case AArch64::MOVIv2s_msl: 1603 case AArch64::MOVIv4s_msl: 1604 case AArch64::MVNIv2s_msl: 1605 case AArch64::MVNIv4s_msl: 1606 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1607 break; 1608 } 1609 1610 return Success; 1611 } 1612 1613 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1614 uint64_t Addr, 1615 const MCDisassembler *Decoder) { 1616 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1617 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1618 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1619 imm |= fieldFromInstruction(insn, 5, 5); 1620 1621 // Tied operands added twice. 1622 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1623 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1624 1625 Inst.addOperand(MCOperand::createImm(imm)); 1626 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1627 1628 return Success; 1629 } 1630 1631 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1632 uint64_t Addr, 1633 const MCDisassembler *Decoder) { 1634 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1635 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1636 imm |= fieldFromInstruction(insn, 29, 2); 1637 1638 // Sign-extend the 21-bit immediate. 1639 if (imm & (1 << (21 - 1))) 1640 imm |= ~((1LL << 21) - 1); 1641 1642 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1643 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4)) 1644 Inst.addOperand(MCOperand::createImm(imm)); 1645 1646 return Success; 1647 } 1648 1649 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1650 uint64_t Addr, 1651 const MCDisassembler *Decoder) { 1652 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1653 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1654 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1655 unsigned S = fieldFromInstruction(insn, 29, 1); 1656 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1657 1658 unsigned ShifterVal = (Imm >> 12) & 3; 1659 unsigned ImmVal = Imm & 0xFFF; 1660 1661 if (ShifterVal != 0 && ShifterVal != 1) 1662 return Fail; 1663 1664 if (Datasize) { 1665 if (Rd == 31 && !S) 1666 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1667 else 1668 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1669 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1670 } else { 1671 if (Rd == 31 && !S) 1672 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1673 else 1674 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1675 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1676 } 1677 1678 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4)) 1679 Inst.addOperand(MCOperand::createImm(ImmVal)); 1680 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1681 return Success; 1682 } 1683 1684 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1685 uint64_t Addr, 1686 const MCDisassembler *Decoder) { 1687 int64_t imm = fieldFromInstruction(insn, 0, 26); 1688 1689 // Sign-extend the 26-bit immediate. 1690 if (imm & (1 << (26 - 1))) 1691 imm |= ~((1LL << 26) - 1); 1692 1693 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4)) 1694 Inst.addOperand(MCOperand::createImm(imm)); 1695 1696 return Success; 1697 } 1698 1699 static DecodeStatus 1700 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1701 const MCDisassembler *Decoder) { 1702 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1703 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1704 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1705 uint64_t pstate_field = (op1 << 3) | op2; 1706 1707 switch (pstate_field) { 1708 case 0x01: // XAFlag 1709 case 0x02: // AXFlag 1710 return Fail; 1711 } 1712 1713 if ((pstate_field == AArch64PState::PAN || 1714 pstate_field == AArch64PState::UAO || 1715 pstate_field == AArch64PState::SSBS) && crm > 1) 1716 return Fail; 1717 1718 Inst.addOperand(MCOperand::createImm(pstate_field)); 1719 Inst.addOperand(MCOperand::createImm(crm)); 1720 1721 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1722 if (PState && 1723 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) 1724 return Success; 1725 return Fail; 1726 } 1727 1728 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1729 uint64_t Addr, 1730 const MCDisassembler *Decoder) { 1731 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1732 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1733 bit |= fieldFromInstruction(insn, 19, 5); 1734 int64_t dst = fieldFromInstruction(insn, 5, 14); 1735 1736 // Sign-extend 14-bit immediate. 1737 if (dst & (1 << (14 - 1))) 1738 dst |= ~((1LL << 14) - 1); 1739 1740 if (fieldFromInstruction(insn, 31, 1) == 0) 1741 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1742 else 1743 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1744 Inst.addOperand(MCOperand::createImm(bit)); 1745 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4)) 1746 Inst.addOperand(MCOperand::createImm(dst)); 1747 1748 return Success; 1749 } 1750 1751 static DecodeStatus 1752 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, 1753 unsigned RegNo, uint64_t Addr, 1754 const MCDisassembler *Decoder) { 1755 // Register number must be even (see CASP instruction) 1756 if (RegNo & 0x1) 1757 return Fail; 1758 1759 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1760 Inst.addOperand(MCOperand::createReg(Reg)); 1761 return Success; 1762 } 1763 1764 static DecodeStatus 1765 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1766 const MCDisassembler *Decoder) { 1767 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1768 AArch64::WSeqPairsClassRegClassID, 1769 RegNo, Addr, Decoder); 1770 } 1771 1772 static DecodeStatus 1773 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1774 const MCDisassembler *Decoder) { 1775 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1776 AArch64::XSeqPairsClassRegClassID, 1777 RegNo, Addr, Decoder); 1778 } 1779 1780 static DecodeStatus 1781 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1782 const MCDisassembler *Decoder) { 1783 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1784 unsigned imm = fieldFromInstruction(insn, 5, 13); 1785 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1786 return Fail; 1787 1788 // The same (tied) operand is added twice to the instruction. 1789 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1790 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1791 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1792 Inst.addOperand(MCOperand::createImm(imm)); 1793 return Success; 1794 } 1795 1796 template <int Bits> 1797 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1798 const MCDisassembler *Decoder) { 1799 if (Imm & ~((1LL << Bits) - 1)) 1800 return Fail; 1801 1802 // Imm is a signed immediate, so sign extend it. 1803 if (Imm & (1 << (Bits - 1))) 1804 Imm |= ~((1LL << Bits) - 1); 1805 1806 Inst.addOperand(MCOperand::createImm(Imm)); 1807 return Success; 1808 } 1809 1810 // Decode 8-bit signed/unsigned immediate for a given element width. 1811 template <int ElementWidth> 1812 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 1813 const MCDisassembler *Decoder) { 1814 unsigned Val = (uint8_t)Imm; 1815 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1816 if (ElementWidth == 8 && Shift) 1817 return Fail; 1818 Inst.addOperand(MCOperand::createImm(Val)); 1819 Inst.addOperand(MCOperand::createImm(Shift)); 1820 return Success; 1821 } 1822 1823 // Decode uimm4 ranged from 1-16. 1824 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1825 uint64_t Addr, 1826 const MCDisassembler *Decoder) { 1827 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1828 return Success; 1829 } 1830 1831 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1832 const MCDisassembler *Decoder) { 1833 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1834 Inst.addOperand(MCOperand::createImm(Imm)); 1835 return Success; 1836 } 1837 return Fail; 1838 } 1839 1840 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 1841 uint64_t Addr, 1842 const MCDisassembler *Decoder) { 1843 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1844 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1845 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1846 1847 // None of the registers may alias: if they do, then the instruction is not 1848 // merely unpredictable but actually entirely unallocated. 1849 if (Rd == Rs || Rs == Rn || Rd == Rn) 1850 return MCDisassembler::Fail; 1851 1852 // All three register operands are written back, so they all appear 1853 // twice in the operand list, once as outputs and once as inputs. 1854 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1855 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1856 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1857 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1858 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1859 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder)) 1860 return MCDisassembler::Fail; 1861 1862 return MCDisassembler::Success; 1863 } 1864 1865 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 1866 uint64_t Addr, 1867 const MCDisassembler *Decoder) { 1868 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1869 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1870 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1871 1872 // None of the registers may alias: if they do, then the instruction is not 1873 // merely unpredictable but actually entirely unallocated. 1874 if (Rd == Rm || Rm == Rn || Rd == Rn) 1875 return MCDisassembler::Fail; 1876 1877 // Rd and Rn (not Rm) register operands are written back, so they appear 1878 // twice in the operand list, once as outputs and once as inputs. 1879 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1880 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1881 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1882 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1883 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder)) 1884 return MCDisassembler::Fail; 1885 1886 return MCDisassembler::Success; 1887 } 1888