1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/TargetRegistry.h" 25 #include "llvm/Support/Compiler.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 122 unsigned RegMask, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const void *Decoder); 179 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, const void *Decoder); 218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 225 unsigned RegNo, 226 uint64_t Addr, 227 const void *Decoder); 228 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 229 uint64_t Address, 230 const void *Decoder); 231 template <int Bits> 232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 233 const void *Decoder); 234 template <int ElementWidth> 235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 236 uint64_t Addr, const void *Decoder); 237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, const void *Decoder); 239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 240 const void *Decoder); 241 242 static bool Check(DecodeStatus &Out, DecodeStatus In) { 243 switch (In) { 244 case MCDisassembler::Success: 245 // Out stays the same. 246 return true; 247 case MCDisassembler::SoftFail: 248 Out = In; 249 return true; 250 case MCDisassembler::Fail: 251 Out = In; 252 return false; 253 } 254 llvm_unreachable("Invalid DecodeStatus!"); 255 } 256 257 #include "AArch64GenDisassemblerTables.inc" 258 #include "AArch64GenInstrInfo.inc" 259 260 #define Success MCDisassembler::Success 261 #define Fail MCDisassembler::Fail 262 #define SoftFail MCDisassembler::SoftFail 263 264 static MCDisassembler *createAArch64Disassembler(const Target &T, 265 const MCSubtargetInfo &STI, 266 MCContext &Ctx) { 267 return new AArch64Disassembler(STI, Ctx); 268 } 269 270 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 271 ArrayRef<uint8_t> Bytes, 272 uint64_t Address, 273 raw_ostream &CS) const { 274 CommentStream = &CS; 275 276 Size = 0; 277 // We want to read exactly 4 bytes of data. 278 if (Bytes.size() < 4) 279 return Fail; 280 Size = 4; 281 282 // Encoded as a small-endian 32-bit word in the stream. 283 uint32_t Insn = 284 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 285 286 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 287 288 for (auto Table : Tables) { 289 DecodeStatus Result = 290 decodeInstruction(Table, MI, Insn, Address, this, STI); 291 292 switch (MI.getOpcode()) { 293 default: 294 break; 295 // For Scalable Matrix Extension (SME) instructions that have an implicit 296 // operand for the accumulator (ZA) which isn't encoded, manually insert 297 // operand. 298 case AArch64::LDR_ZA: 299 case AArch64::STR_ZA: { 300 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 301 // Spill and fill instructions have a single immediate used for both the 302 // vector select offset and optional memory offset. Replicate the decoded 303 // immediate. 304 const MCOperand &Imm4Op = MI.getOperand(2); 305 assert(Imm4Op.isImm() && "Unexpected operand type!"); 306 MI.addOperand(Imm4Op); 307 break; 308 } 309 case AArch64::LD1_MXIPXX_H_B: 310 case AArch64::LD1_MXIPXX_V_B: 311 case AArch64::ST1_MXIPXX_H_B: 312 case AArch64::ST1_MXIPXX_V_B: 313 case AArch64::INSERT_MXIPZ_H_B: 314 case AArch64::INSERT_MXIPZ_V_B: 315 // e.g. 316 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 317 // ^ insert implicit 8-bit element tile 318 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 319 break; 320 case AArch64::EXTRACT_ZPMXI_H_B: 321 case AArch64::EXTRACT_ZPMXI_V_B: 322 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 323 // ^ insert implicit 8-bit element tile 324 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 325 break; 326 case AArch64::LD1_MXIPXX_H_Q: 327 case AArch64::LD1_MXIPXX_V_Q: 328 case AArch64::ST1_MXIPXX_H_Q: 329 case AArch64::ST1_MXIPXX_V_Q: 330 // 128-bit load/store have implicit zero vector index. 331 MI.insert(MI.begin()+2, MCOperand::createImm(0)); 332 break; 333 // 128-bit mova have implicit zero vector index. 334 case AArch64::INSERT_MXIPZ_H_Q: 335 case AArch64::INSERT_MXIPZ_V_Q: 336 MI.insert(MI.begin()+2, MCOperand::createImm(0)); 337 break; 338 case AArch64::EXTRACT_ZPMXI_H_Q: 339 case AArch64::EXTRACT_ZPMXI_V_Q: 340 MI.addOperand(MCOperand::createImm(0)); 341 break; 342 case AArch64::SMOVvi8to32_idx0: 343 case AArch64::SMOVvi8to64_idx0: 344 case AArch64::SMOVvi16to32_idx0: 345 case AArch64::SMOVvi16to64_idx0: 346 case AArch64::SMOVvi32to64_idx0: 347 case AArch64::UMOVvi8_idx0: 348 case AArch64::UMOVvi16_idx0: 349 case AArch64::UMOVvi32_idx0: 350 case AArch64::UMOVvi64_idx0: 351 MI.addOperand(MCOperand::createImm(0)); 352 break; 353 } 354 355 if (Result != MCDisassembler::Fail) 356 return Result; 357 } 358 359 return MCDisassembler::Fail; 360 } 361 362 static MCSymbolizer * 363 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 364 LLVMSymbolLookupCallback SymbolLookUp, 365 void *DisInfo, MCContext *Ctx, 366 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 367 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 368 SymbolLookUp, DisInfo); 369 } 370 371 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 372 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 373 createAArch64Disassembler); 374 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 375 createAArch64Disassembler); 376 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 377 createAArch64ExternalSymbolizer); 378 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 379 createAArch64ExternalSymbolizer); 380 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 381 createAArch64Disassembler); 382 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 383 createAArch64ExternalSymbolizer); 384 385 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 386 createAArch64Disassembler); 387 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 388 createAArch64ExternalSymbolizer); 389 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 390 createAArch64Disassembler); 391 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 392 createAArch64ExternalSymbolizer); 393 } 394 395 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 396 uint64_t Addr, 397 const void *Decoder) { 398 if (RegNo > 31) 399 return Fail; 400 401 unsigned Register = 402 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 403 Inst.addOperand(MCOperand::createReg(Register)); 404 return Success; 405 } 406 407 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 408 uint64_t Addr, 409 const void *Decoder) { 410 if (RegNo > 15) 411 return Fail; 412 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 413 } 414 415 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 416 uint64_t Addr, 417 const void *Decoder) { 418 if (RegNo > 31) 419 return Fail; 420 421 unsigned Register = 422 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 423 Inst.addOperand(MCOperand::createReg(Register)); 424 return Success; 425 } 426 427 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 428 uint64_t Addr, 429 const void *Decoder) { 430 if (RegNo > 31) 431 return Fail; 432 433 unsigned Register = 434 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 435 Inst.addOperand(MCOperand::createReg(Register)); 436 return Success; 437 } 438 439 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 440 uint64_t Addr, 441 const void *Decoder) { 442 if (RegNo > 31) 443 return Fail; 444 445 unsigned Register = 446 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 447 Inst.addOperand(MCOperand::createReg(Register)); 448 return Success; 449 } 450 451 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 452 uint64_t Addr, 453 const void *Decoder) { 454 if (RegNo > 31) 455 return Fail; 456 457 unsigned Register = 458 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 459 Inst.addOperand(MCOperand::createReg(Register)); 460 return Success; 461 } 462 463 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 464 uint64_t Addr, 465 const void *Decoder) { 466 if (RegNo > 30) 467 return Fail; 468 469 unsigned Register = 470 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 471 RegNo); 472 Inst.addOperand(MCOperand::createReg(Register)); 473 return Success; 474 } 475 476 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 477 uint64_t Addr, 478 const void *Decoder) { 479 if (RegNo > 31) 480 return Fail; 481 482 unsigned Register = 483 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 484 Inst.addOperand(MCOperand::createReg(Register)); 485 return Success; 486 } 487 488 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 489 unsigned RegNo, 490 uint64_t Address, 491 const void *Decoder) { 492 if (RegNo > 22) 493 return Fail; 494 if (RegNo & 1) 495 return Fail; 496 497 unsigned Register = 498 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 499 RegNo >> 1); 500 Inst.addOperand(MCOperand::createReg(Register)); 501 return Success; 502 } 503 504 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 505 uint64_t Addr, 506 const void *Decoder) { 507 if (RegNo > 31) 508 return Fail; 509 unsigned Register = 510 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 511 Inst.addOperand(MCOperand::createReg(Register)); 512 return Success; 513 } 514 515 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 516 unsigned RegNo, 517 uint64_t Addr, 518 const void *Decoder) { 519 if (RegNo > 3) 520 return Fail; 521 522 unsigned Register = 523 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 524 .getRegister(RegNo); 525 Inst.addOperand(MCOperand::createReg(Register)); 526 return Success; 527 } 528 529 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 530 uint64_t Addr, 531 const void *Decoder) { 532 if (RegNo > 31) 533 return Fail; 534 535 unsigned Register = 536 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 537 Inst.addOperand(MCOperand::createReg(Register)); 538 return Success; 539 } 540 541 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 542 uint64_t Addr, 543 const void *Decoder) { 544 if (RegNo > 31) 545 return Fail; 546 547 unsigned Register = 548 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 549 Inst.addOperand(MCOperand::createReg(Register)); 550 return Success; 551 } 552 553 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 554 uint64_t Address, 555 const void* Decoder) { 556 if (RegNo > 31) 557 return Fail; 558 559 unsigned Register = 560 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 561 Inst.addOperand(MCOperand::createReg(Register)); 562 return Success; 563 } 564 565 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 566 uint64_t Address, 567 const void *Decoder) { 568 if (RegNo > 15) 569 return Fail; 570 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 571 } 572 573 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 574 uint64_t Address, 575 const void *Decoder) { 576 if (RegNo > 7) 577 return Fail; 578 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 579 } 580 581 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 582 uint64_t Address, 583 const void* Decoder) { 584 if (RegNo > 31) 585 return Fail; 586 unsigned Register = 587 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 588 Inst.addOperand(MCOperand::createReg(Register)); 589 return Success; 590 } 591 592 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 593 uint64_t Address, 594 const void* Decoder) { 595 if (RegNo > 31) 596 return Fail; 597 unsigned Register = 598 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 599 Inst.addOperand(MCOperand::createReg(Register)); 600 return Success; 601 } 602 603 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 604 uint64_t Address, 605 const void* Decoder) { 606 if (RegNo > 31) 607 return Fail; 608 unsigned Register = 609 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 610 Inst.addOperand(MCOperand::createReg(Register)); 611 return Success; 612 } 613 614 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 615 unsigned RegMask, 616 uint64_t Address, 617 const void *Decoder) { 618 if (RegMask > 0xFF) 619 return Fail; 620 Inst.addOperand(MCOperand::createImm(RegMask)); 621 return Success; 622 } 623 624 static const SmallVector<SmallVector<unsigned, 16>, 5> 625 MatrixZATileDecoderTable = { 626 {AArch64::ZAB0}, 627 {AArch64::ZAH0, AArch64::ZAH1}, 628 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 629 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 630 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 631 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 632 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 633 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 634 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 635 636 template <unsigned NumBitsForTile> 637 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 638 uint64_t Address, const void *Decoder) { 639 unsigned LastReg = (1 << NumBitsForTile) - 1; 640 if (RegNo > LastReg) 641 return Fail; 642 Inst.addOperand( 643 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 644 return Success; 645 } 646 647 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 648 uint64_t Addr, const void *Decoder) { 649 if (RegNo > 15) 650 return Fail; 651 652 unsigned Register = 653 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 654 Inst.addOperand(MCOperand::createReg(Register)); 655 return Success; 656 } 657 658 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 659 uint64_t Addr, 660 const void* Decoder) { 661 if (RegNo > 7) 662 return Fail; 663 664 // Just reuse the PPR decode table 665 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 666 } 667 668 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 669 uint64_t Addr, const void *Decoder) { 670 if (RegNo > 31) 671 return Fail; 672 unsigned Register = 673 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 674 Inst.addOperand(MCOperand::createReg(Register)); 675 return Success; 676 } 677 678 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 679 uint64_t Addr, const void *Decoder) { 680 if (RegNo > 31) 681 return Fail; 682 unsigned Register = 683 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 684 Inst.addOperand(MCOperand::createReg(Register)); 685 return Success; 686 } 687 688 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 689 uint64_t Addr, 690 const void *Decoder) { 691 if (RegNo > 31) 692 return Fail; 693 unsigned Register = 694 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 695 Inst.addOperand(MCOperand::createReg(Register)); 696 return Success; 697 } 698 699 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 700 uint64_t Addr, const void *Decoder) { 701 if (RegNo > 31) 702 return Fail; 703 unsigned Register = 704 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 705 Inst.addOperand(MCOperand::createReg(Register)); 706 return Success; 707 } 708 709 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 710 uint64_t Addr, const void *Decoder) { 711 if (RegNo > 31) 712 return Fail; 713 unsigned Register = 714 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 715 Inst.addOperand(MCOperand::createReg(Register)); 716 return Success; 717 } 718 719 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 720 uint64_t Addr, 721 const void *Decoder) { 722 if (RegNo > 31) 723 return Fail; 724 unsigned Register = 725 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 726 Inst.addOperand(MCOperand::createReg(Register)); 727 return Success; 728 } 729 730 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 731 uint64_t Addr, 732 const void *Decoder) { 733 // scale{5} is asserted as 1 in tblgen. 734 Imm |= 0x20; 735 Inst.addOperand(MCOperand::createImm(64 - Imm)); 736 return Success; 737 } 738 739 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 740 uint64_t Addr, 741 const void *Decoder) { 742 Inst.addOperand(MCOperand::createImm(64 - Imm)); 743 return Success; 744 } 745 746 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 747 uint64_t Addr, const void *Decoder) { 748 int64_t ImmVal = Imm; 749 const AArch64Disassembler *Dis = 750 static_cast<const AArch64Disassembler *>(Decoder); 751 752 // Sign-extend 19-bit immediate. 753 if (ImmVal & (1 << (19 - 1))) 754 ImmVal |= ~((1LL << 19) - 1); 755 756 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 757 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 758 Inst.addOperand(MCOperand::createImm(ImmVal)); 759 return Success; 760 } 761 762 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 763 uint64_t Address, const void *Decoder) { 764 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 765 Inst.addOperand(MCOperand::createImm(Imm & 1)); 766 return Success; 767 } 768 769 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 770 uint64_t Address, 771 const void *Decoder) { 772 Inst.addOperand(MCOperand::createImm(Imm)); 773 774 // Every system register in the encoding space is valid with the syntax 775 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 776 return Success; 777 } 778 779 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 780 uint64_t Address, 781 const void *Decoder) { 782 Inst.addOperand(MCOperand::createImm(Imm)); 783 784 return Success; 785 } 786 787 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 788 uint64_t Address, 789 const void *Decoder) { 790 // This decoder exists to add the dummy Lane operand to the MCInst, which must 791 // be 1 in assembly but has no other real manifestation. 792 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 793 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 794 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 795 796 if (IsToVec) { 797 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 798 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 799 } else { 800 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 801 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 802 } 803 804 // Add the lane 805 Inst.addOperand(MCOperand::createImm(1)); 806 807 return Success; 808 } 809 810 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 811 unsigned Add) { 812 Inst.addOperand(MCOperand::createImm(Add - Imm)); 813 return Success; 814 } 815 816 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 817 unsigned Add) { 818 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 819 return Success; 820 } 821 822 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 823 uint64_t Addr, const void *Decoder) { 824 return DecodeVecShiftRImm(Inst, Imm, 64); 825 } 826 827 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 828 uint64_t Addr, 829 const void *Decoder) { 830 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 831 } 832 833 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 834 uint64_t Addr, const void *Decoder) { 835 return DecodeVecShiftRImm(Inst, Imm, 32); 836 } 837 838 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 839 uint64_t Addr, 840 const void *Decoder) { 841 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 842 } 843 844 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 845 uint64_t Addr, const void *Decoder) { 846 return DecodeVecShiftRImm(Inst, Imm, 16); 847 } 848 849 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 850 uint64_t Addr, 851 const void *Decoder) { 852 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 853 } 854 855 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 856 uint64_t Addr, const void *Decoder) { 857 return DecodeVecShiftRImm(Inst, Imm, 8); 858 } 859 860 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 861 uint64_t Addr, const void *Decoder) { 862 return DecodeVecShiftLImm(Inst, Imm, 64); 863 } 864 865 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 866 uint64_t Addr, const void *Decoder) { 867 return DecodeVecShiftLImm(Inst, Imm, 32); 868 } 869 870 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 871 uint64_t Addr, const void *Decoder) { 872 return DecodeVecShiftLImm(Inst, Imm, 16); 873 } 874 875 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 876 uint64_t Addr, const void *Decoder) { 877 return DecodeVecShiftLImm(Inst, Imm, 8); 878 } 879 880 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 881 uint64_t Addr, 882 const void *Decoder) { 883 unsigned Rd = fieldFromInstruction(insn, 0, 5); 884 unsigned Rn = fieldFromInstruction(insn, 5, 5); 885 unsigned Rm = fieldFromInstruction(insn, 16, 5); 886 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 887 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 888 unsigned shift = (shiftHi << 6) | shiftLo; 889 switch (Inst.getOpcode()) { 890 default: 891 return Fail; 892 case AArch64::ADDWrs: 893 case AArch64::ADDSWrs: 894 case AArch64::SUBWrs: 895 case AArch64::SUBSWrs: 896 // if shift == '11' then ReservedValue() 897 if (shiftHi == 0x3) 898 return Fail; 899 LLVM_FALLTHROUGH; 900 case AArch64::ANDWrs: 901 case AArch64::ANDSWrs: 902 case AArch64::BICWrs: 903 case AArch64::BICSWrs: 904 case AArch64::ORRWrs: 905 case AArch64::ORNWrs: 906 case AArch64::EORWrs: 907 case AArch64::EONWrs: { 908 // if sf == '0' and imm6<5> == '1' then ReservedValue() 909 if (shiftLo >> 5 == 1) 910 return Fail; 911 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 912 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 913 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 914 break; 915 } 916 case AArch64::ADDXrs: 917 case AArch64::ADDSXrs: 918 case AArch64::SUBXrs: 919 case AArch64::SUBSXrs: 920 // if shift == '11' then ReservedValue() 921 if (shiftHi == 0x3) 922 return Fail; 923 LLVM_FALLTHROUGH; 924 case AArch64::ANDXrs: 925 case AArch64::ANDSXrs: 926 case AArch64::BICXrs: 927 case AArch64::BICSXrs: 928 case AArch64::ORRXrs: 929 case AArch64::ORNXrs: 930 case AArch64::EORXrs: 931 case AArch64::EONXrs: 932 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 933 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 934 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 935 break; 936 } 937 938 Inst.addOperand(MCOperand::createImm(shift)); 939 return Success; 940 } 941 942 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 943 uint64_t Addr, 944 const void *Decoder) { 945 unsigned Rd = fieldFromInstruction(insn, 0, 5); 946 unsigned imm = fieldFromInstruction(insn, 5, 16); 947 unsigned shift = fieldFromInstruction(insn, 21, 2); 948 shift <<= 4; 949 switch (Inst.getOpcode()) { 950 default: 951 return Fail; 952 case AArch64::MOVZWi: 953 case AArch64::MOVNWi: 954 case AArch64::MOVKWi: 955 if (shift & (1U << 5)) 956 return Fail; 957 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 958 break; 959 case AArch64::MOVZXi: 960 case AArch64::MOVNXi: 961 case AArch64::MOVKXi: 962 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 963 break; 964 } 965 966 if (Inst.getOpcode() == AArch64::MOVKWi || 967 Inst.getOpcode() == AArch64::MOVKXi) 968 Inst.addOperand(Inst.getOperand(0)); 969 970 Inst.addOperand(MCOperand::createImm(imm)); 971 Inst.addOperand(MCOperand::createImm(shift)); 972 return Success; 973 } 974 975 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 976 uint64_t Addr, 977 const void *Decoder) { 978 unsigned Rt = fieldFromInstruction(insn, 0, 5); 979 unsigned Rn = fieldFromInstruction(insn, 5, 5); 980 unsigned offset = fieldFromInstruction(insn, 10, 12); 981 const AArch64Disassembler *Dis = 982 static_cast<const AArch64Disassembler *>(Decoder); 983 984 switch (Inst.getOpcode()) { 985 default: 986 return Fail; 987 case AArch64::PRFMui: 988 // Rt is an immediate in prefetch. 989 Inst.addOperand(MCOperand::createImm(Rt)); 990 break; 991 case AArch64::STRBBui: 992 case AArch64::LDRBBui: 993 case AArch64::LDRSBWui: 994 case AArch64::STRHHui: 995 case AArch64::LDRHHui: 996 case AArch64::LDRSHWui: 997 case AArch64::STRWui: 998 case AArch64::LDRWui: 999 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1000 break; 1001 case AArch64::LDRSBXui: 1002 case AArch64::LDRSHXui: 1003 case AArch64::LDRSWui: 1004 case AArch64::STRXui: 1005 case AArch64::LDRXui: 1006 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1007 break; 1008 case AArch64::LDRQui: 1009 case AArch64::STRQui: 1010 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1011 break; 1012 case AArch64::LDRDui: 1013 case AArch64::STRDui: 1014 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1015 break; 1016 case AArch64::LDRSui: 1017 case AArch64::STRSui: 1018 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1019 break; 1020 case AArch64::LDRHui: 1021 case AArch64::STRHui: 1022 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1023 break; 1024 case AArch64::LDRBui: 1025 case AArch64::STRBui: 1026 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1027 break; 1028 } 1029 1030 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1031 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1032 Inst.addOperand(MCOperand::createImm(offset)); 1033 return Success; 1034 } 1035 1036 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1037 uint64_t Addr, 1038 const void *Decoder) { 1039 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1040 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1041 int64_t offset = fieldFromInstruction(insn, 12, 9); 1042 1043 // offset is a 9-bit signed immediate, so sign extend it to 1044 // fill the unsigned. 1045 if (offset & (1 << (9 - 1))) 1046 offset |= ~((1LL << 9) - 1); 1047 1048 // First operand is always the writeback to the address register, if needed. 1049 switch (Inst.getOpcode()) { 1050 default: 1051 break; 1052 case AArch64::LDRSBWpre: 1053 case AArch64::LDRSHWpre: 1054 case AArch64::STRBBpre: 1055 case AArch64::LDRBBpre: 1056 case AArch64::STRHHpre: 1057 case AArch64::LDRHHpre: 1058 case AArch64::STRWpre: 1059 case AArch64::LDRWpre: 1060 case AArch64::LDRSBWpost: 1061 case AArch64::LDRSHWpost: 1062 case AArch64::STRBBpost: 1063 case AArch64::LDRBBpost: 1064 case AArch64::STRHHpost: 1065 case AArch64::LDRHHpost: 1066 case AArch64::STRWpost: 1067 case AArch64::LDRWpost: 1068 case AArch64::LDRSBXpre: 1069 case AArch64::LDRSHXpre: 1070 case AArch64::STRXpre: 1071 case AArch64::LDRSWpre: 1072 case AArch64::LDRXpre: 1073 case AArch64::LDRSBXpost: 1074 case AArch64::LDRSHXpost: 1075 case AArch64::STRXpost: 1076 case AArch64::LDRSWpost: 1077 case AArch64::LDRXpost: 1078 case AArch64::LDRQpre: 1079 case AArch64::STRQpre: 1080 case AArch64::LDRQpost: 1081 case AArch64::STRQpost: 1082 case AArch64::LDRDpre: 1083 case AArch64::STRDpre: 1084 case AArch64::LDRDpost: 1085 case AArch64::STRDpost: 1086 case AArch64::LDRSpre: 1087 case AArch64::STRSpre: 1088 case AArch64::LDRSpost: 1089 case AArch64::STRSpost: 1090 case AArch64::LDRHpre: 1091 case AArch64::STRHpre: 1092 case AArch64::LDRHpost: 1093 case AArch64::STRHpost: 1094 case AArch64::LDRBpre: 1095 case AArch64::STRBpre: 1096 case AArch64::LDRBpost: 1097 case AArch64::STRBpost: 1098 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1099 break; 1100 } 1101 1102 switch (Inst.getOpcode()) { 1103 default: 1104 return Fail; 1105 case AArch64::PRFUMi: 1106 // Rt is an immediate in prefetch. 1107 Inst.addOperand(MCOperand::createImm(Rt)); 1108 break; 1109 case AArch64::STURBBi: 1110 case AArch64::LDURBBi: 1111 case AArch64::LDURSBWi: 1112 case AArch64::STURHHi: 1113 case AArch64::LDURHHi: 1114 case AArch64::LDURSHWi: 1115 case AArch64::STURWi: 1116 case AArch64::LDURWi: 1117 case AArch64::LDTRSBWi: 1118 case AArch64::LDTRSHWi: 1119 case AArch64::STTRWi: 1120 case AArch64::LDTRWi: 1121 case AArch64::STTRHi: 1122 case AArch64::LDTRHi: 1123 case AArch64::LDTRBi: 1124 case AArch64::STTRBi: 1125 case AArch64::LDRSBWpre: 1126 case AArch64::LDRSHWpre: 1127 case AArch64::STRBBpre: 1128 case AArch64::LDRBBpre: 1129 case AArch64::STRHHpre: 1130 case AArch64::LDRHHpre: 1131 case AArch64::STRWpre: 1132 case AArch64::LDRWpre: 1133 case AArch64::LDRSBWpost: 1134 case AArch64::LDRSHWpost: 1135 case AArch64::STRBBpost: 1136 case AArch64::LDRBBpost: 1137 case AArch64::STRHHpost: 1138 case AArch64::LDRHHpost: 1139 case AArch64::STRWpost: 1140 case AArch64::LDRWpost: 1141 case AArch64::STLURBi: 1142 case AArch64::STLURHi: 1143 case AArch64::STLURWi: 1144 case AArch64::LDAPURBi: 1145 case AArch64::LDAPURSBWi: 1146 case AArch64::LDAPURHi: 1147 case AArch64::LDAPURSHWi: 1148 case AArch64::LDAPURi: 1149 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1150 break; 1151 case AArch64::LDURSBXi: 1152 case AArch64::LDURSHXi: 1153 case AArch64::LDURSWi: 1154 case AArch64::STURXi: 1155 case AArch64::LDURXi: 1156 case AArch64::LDTRSBXi: 1157 case AArch64::LDTRSHXi: 1158 case AArch64::LDTRSWi: 1159 case AArch64::STTRXi: 1160 case AArch64::LDTRXi: 1161 case AArch64::LDRSBXpre: 1162 case AArch64::LDRSHXpre: 1163 case AArch64::STRXpre: 1164 case AArch64::LDRSWpre: 1165 case AArch64::LDRXpre: 1166 case AArch64::LDRSBXpost: 1167 case AArch64::LDRSHXpost: 1168 case AArch64::STRXpost: 1169 case AArch64::LDRSWpost: 1170 case AArch64::LDRXpost: 1171 case AArch64::LDAPURSWi: 1172 case AArch64::LDAPURSHXi: 1173 case AArch64::LDAPURSBXi: 1174 case AArch64::STLURXi: 1175 case AArch64::LDAPURXi: 1176 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1177 break; 1178 case AArch64::LDURQi: 1179 case AArch64::STURQi: 1180 case AArch64::LDRQpre: 1181 case AArch64::STRQpre: 1182 case AArch64::LDRQpost: 1183 case AArch64::STRQpost: 1184 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1185 break; 1186 case AArch64::LDURDi: 1187 case AArch64::STURDi: 1188 case AArch64::LDRDpre: 1189 case AArch64::STRDpre: 1190 case AArch64::LDRDpost: 1191 case AArch64::STRDpost: 1192 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1193 break; 1194 case AArch64::LDURSi: 1195 case AArch64::STURSi: 1196 case AArch64::LDRSpre: 1197 case AArch64::STRSpre: 1198 case AArch64::LDRSpost: 1199 case AArch64::STRSpost: 1200 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1201 break; 1202 case AArch64::LDURHi: 1203 case AArch64::STURHi: 1204 case AArch64::LDRHpre: 1205 case AArch64::STRHpre: 1206 case AArch64::LDRHpost: 1207 case AArch64::STRHpost: 1208 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1209 break; 1210 case AArch64::LDURBi: 1211 case AArch64::STURBi: 1212 case AArch64::LDRBpre: 1213 case AArch64::STRBpre: 1214 case AArch64::LDRBpost: 1215 case AArch64::STRBpost: 1216 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1217 break; 1218 } 1219 1220 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1221 Inst.addOperand(MCOperand::createImm(offset)); 1222 1223 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1224 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1225 bool IsFP = fieldFromInstruction(insn, 26, 1); 1226 1227 // Cannot write back to a transfer register (but xzr != sp). 1228 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1229 return SoftFail; 1230 1231 return Success; 1232 } 1233 1234 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1235 uint64_t Addr, 1236 const void *Decoder) { 1237 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1238 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1239 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1240 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1241 1242 unsigned Opcode = Inst.getOpcode(); 1243 switch (Opcode) { 1244 default: 1245 return Fail; 1246 case AArch64::STLXRW: 1247 case AArch64::STLXRB: 1248 case AArch64::STLXRH: 1249 case AArch64::STXRW: 1250 case AArch64::STXRB: 1251 case AArch64::STXRH: 1252 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1253 LLVM_FALLTHROUGH; 1254 case AArch64::LDARW: 1255 case AArch64::LDARB: 1256 case AArch64::LDARH: 1257 case AArch64::LDAXRW: 1258 case AArch64::LDAXRB: 1259 case AArch64::LDAXRH: 1260 case AArch64::LDXRW: 1261 case AArch64::LDXRB: 1262 case AArch64::LDXRH: 1263 case AArch64::STLRW: 1264 case AArch64::STLRB: 1265 case AArch64::STLRH: 1266 case AArch64::STLLRW: 1267 case AArch64::STLLRB: 1268 case AArch64::STLLRH: 1269 case AArch64::LDLARW: 1270 case AArch64::LDLARB: 1271 case AArch64::LDLARH: 1272 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1273 break; 1274 case AArch64::STLXRX: 1275 case AArch64::STXRX: 1276 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1277 LLVM_FALLTHROUGH; 1278 case AArch64::LDARX: 1279 case AArch64::LDAXRX: 1280 case AArch64::LDXRX: 1281 case AArch64::STLRX: 1282 case AArch64::LDLARX: 1283 case AArch64::STLLRX: 1284 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1285 break; 1286 case AArch64::STLXPW: 1287 case AArch64::STXPW: 1288 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1289 LLVM_FALLTHROUGH; 1290 case AArch64::LDAXPW: 1291 case AArch64::LDXPW: 1292 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1293 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1294 break; 1295 case AArch64::STLXPX: 1296 case AArch64::STXPX: 1297 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1298 LLVM_FALLTHROUGH; 1299 case AArch64::LDAXPX: 1300 case AArch64::LDXPX: 1301 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1302 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1303 break; 1304 } 1305 1306 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1307 1308 // You shouldn't load to the same register twice in an instruction... 1309 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1310 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1311 Rt == Rt2) 1312 return SoftFail; 1313 1314 return Success; 1315 } 1316 1317 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1318 uint64_t Addr, 1319 const void *Decoder) { 1320 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1321 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1322 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1323 int64_t offset = fieldFromInstruction(insn, 15, 7); 1324 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1325 1326 // offset is a 7-bit signed immediate, so sign extend it to 1327 // fill the unsigned. 1328 if (offset & (1 << (7 - 1))) 1329 offset |= ~((1LL << 7) - 1); 1330 1331 unsigned Opcode = Inst.getOpcode(); 1332 bool NeedsDisjointWritebackTransfer = false; 1333 1334 // First operand is always writeback of base register. 1335 switch (Opcode) { 1336 default: 1337 break; 1338 case AArch64::LDPXpost: 1339 case AArch64::STPXpost: 1340 case AArch64::LDPSWpost: 1341 case AArch64::LDPXpre: 1342 case AArch64::STPXpre: 1343 case AArch64::LDPSWpre: 1344 case AArch64::LDPWpost: 1345 case AArch64::STPWpost: 1346 case AArch64::LDPWpre: 1347 case AArch64::STPWpre: 1348 case AArch64::LDPQpost: 1349 case AArch64::STPQpost: 1350 case AArch64::LDPQpre: 1351 case AArch64::STPQpre: 1352 case AArch64::LDPDpost: 1353 case AArch64::STPDpost: 1354 case AArch64::LDPDpre: 1355 case AArch64::STPDpre: 1356 case AArch64::LDPSpost: 1357 case AArch64::STPSpost: 1358 case AArch64::LDPSpre: 1359 case AArch64::STPSpre: 1360 case AArch64::STGPpre: 1361 case AArch64::STGPpost: 1362 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1363 break; 1364 } 1365 1366 switch (Opcode) { 1367 default: 1368 return Fail; 1369 case AArch64::LDPXpost: 1370 case AArch64::STPXpost: 1371 case AArch64::LDPSWpost: 1372 case AArch64::LDPXpre: 1373 case AArch64::STPXpre: 1374 case AArch64::LDPSWpre: 1375 case AArch64::STGPpre: 1376 case AArch64::STGPpost: 1377 NeedsDisjointWritebackTransfer = true; 1378 LLVM_FALLTHROUGH; 1379 case AArch64::LDNPXi: 1380 case AArch64::STNPXi: 1381 case AArch64::LDPXi: 1382 case AArch64::STPXi: 1383 case AArch64::LDPSWi: 1384 case AArch64::STGPi: 1385 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1386 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1387 break; 1388 case AArch64::LDPWpost: 1389 case AArch64::STPWpost: 1390 case AArch64::LDPWpre: 1391 case AArch64::STPWpre: 1392 NeedsDisjointWritebackTransfer = true; 1393 LLVM_FALLTHROUGH; 1394 case AArch64::LDNPWi: 1395 case AArch64::STNPWi: 1396 case AArch64::LDPWi: 1397 case AArch64::STPWi: 1398 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1399 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1400 break; 1401 case AArch64::LDNPQi: 1402 case AArch64::STNPQi: 1403 case AArch64::LDPQpost: 1404 case AArch64::STPQpost: 1405 case AArch64::LDPQi: 1406 case AArch64::STPQi: 1407 case AArch64::LDPQpre: 1408 case AArch64::STPQpre: 1409 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1410 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1411 break; 1412 case AArch64::LDNPDi: 1413 case AArch64::STNPDi: 1414 case AArch64::LDPDpost: 1415 case AArch64::STPDpost: 1416 case AArch64::LDPDi: 1417 case AArch64::STPDi: 1418 case AArch64::LDPDpre: 1419 case AArch64::STPDpre: 1420 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1421 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1422 break; 1423 case AArch64::LDNPSi: 1424 case AArch64::STNPSi: 1425 case AArch64::LDPSpost: 1426 case AArch64::STPSpost: 1427 case AArch64::LDPSi: 1428 case AArch64::STPSi: 1429 case AArch64::LDPSpre: 1430 case AArch64::STPSpre: 1431 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1432 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1433 break; 1434 } 1435 1436 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1437 Inst.addOperand(MCOperand::createImm(offset)); 1438 1439 // You shouldn't load to the same register twice in an instruction... 1440 if (IsLoad && Rt == Rt2) 1441 return SoftFail; 1442 1443 // ... or do any operation that writes-back to a transfer register. But note 1444 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1445 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1446 return SoftFail; 1447 1448 return Success; 1449 } 1450 1451 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1452 uint64_t Addr, 1453 const void *Decoder) { 1454 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1455 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1456 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1457 fieldFromInstruction(insn, 12, 9); 1458 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1459 1460 switch (Inst.getOpcode()) { 1461 default: 1462 return Fail; 1463 case AArch64::LDRAAwriteback: 1464 case AArch64::LDRABwriteback: 1465 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1466 Decoder); 1467 break; 1468 case AArch64::LDRAAindexed: 1469 case AArch64::LDRABindexed: 1470 break; 1471 } 1472 1473 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1474 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1475 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1476 1477 if (writeback && Rt == Rn && Rn != 31) { 1478 return SoftFail; 1479 } 1480 1481 return Success; 1482 } 1483 1484 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1485 uint64_t Addr, 1486 const void *Decoder) { 1487 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1488 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1489 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1490 unsigned extend = fieldFromInstruction(insn, 10, 6); 1491 1492 unsigned shift = extend & 0x7; 1493 if (shift > 4) 1494 return Fail; 1495 1496 switch (Inst.getOpcode()) { 1497 default: 1498 return Fail; 1499 case AArch64::ADDWrx: 1500 case AArch64::SUBWrx: 1501 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1502 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1503 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1504 break; 1505 case AArch64::ADDSWrx: 1506 case AArch64::SUBSWrx: 1507 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1508 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1509 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1510 break; 1511 case AArch64::ADDXrx: 1512 case AArch64::SUBXrx: 1513 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1514 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1515 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1516 break; 1517 case AArch64::ADDSXrx: 1518 case AArch64::SUBSXrx: 1519 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1520 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1521 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1522 break; 1523 case AArch64::ADDXrx64: 1524 case AArch64::SUBXrx64: 1525 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1526 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1527 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1528 break; 1529 case AArch64::SUBSXrx64: 1530 case AArch64::ADDSXrx64: 1531 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1532 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1533 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1534 break; 1535 } 1536 1537 Inst.addOperand(MCOperand::createImm(extend)); 1538 return Success; 1539 } 1540 1541 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1542 uint64_t Addr, 1543 const void *Decoder) { 1544 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1545 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1546 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1547 unsigned imm; 1548 1549 if (Datasize) { 1550 if (Inst.getOpcode() == AArch64::ANDSXri) 1551 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1552 else 1553 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1554 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1555 imm = fieldFromInstruction(insn, 10, 13); 1556 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1557 return Fail; 1558 } else { 1559 if (Inst.getOpcode() == AArch64::ANDSWri) 1560 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1561 else 1562 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1563 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1564 imm = fieldFromInstruction(insn, 10, 12); 1565 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1566 return Fail; 1567 } 1568 Inst.addOperand(MCOperand::createImm(imm)); 1569 return Success; 1570 } 1571 1572 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1573 uint64_t Addr, 1574 const void *Decoder) { 1575 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1576 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1577 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1578 imm |= fieldFromInstruction(insn, 5, 5); 1579 1580 if (Inst.getOpcode() == AArch64::MOVID) 1581 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1582 else 1583 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1584 1585 Inst.addOperand(MCOperand::createImm(imm)); 1586 1587 switch (Inst.getOpcode()) { 1588 default: 1589 break; 1590 case AArch64::MOVIv4i16: 1591 case AArch64::MOVIv8i16: 1592 case AArch64::MVNIv4i16: 1593 case AArch64::MVNIv8i16: 1594 case AArch64::MOVIv2i32: 1595 case AArch64::MOVIv4i32: 1596 case AArch64::MVNIv2i32: 1597 case AArch64::MVNIv4i32: 1598 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1599 break; 1600 case AArch64::MOVIv2s_msl: 1601 case AArch64::MOVIv4s_msl: 1602 case AArch64::MVNIv2s_msl: 1603 case AArch64::MVNIv4s_msl: 1604 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1605 break; 1606 } 1607 1608 return Success; 1609 } 1610 1611 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1612 uint64_t Addr, 1613 const void *Decoder) { 1614 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1615 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1616 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1617 imm |= fieldFromInstruction(insn, 5, 5); 1618 1619 // Tied operands added twice. 1620 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1621 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1622 1623 Inst.addOperand(MCOperand::createImm(imm)); 1624 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1625 1626 return Success; 1627 } 1628 1629 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1630 uint64_t Addr, const void *Decoder) { 1631 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1632 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1633 imm |= fieldFromInstruction(insn, 29, 2); 1634 const AArch64Disassembler *Dis = 1635 static_cast<const AArch64Disassembler *>(Decoder); 1636 1637 // Sign-extend the 21-bit immediate. 1638 if (imm & (1 << (21 - 1))) 1639 imm |= ~((1LL << 21) - 1); 1640 1641 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1642 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1643 Inst.addOperand(MCOperand::createImm(imm)); 1644 1645 return Success; 1646 } 1647 1648 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1649 uint64_t Addr, const void *Decoder) { 1650 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1651 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1652 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1653 unsigned S = fieldFromInstruction(insn, 29, 1); 1654 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1655 1656 unsigned ShifterVal = (Imm >> 12) & 3; 1657 unsigned ImmVal = Imm & 0xFFF; 1658 const AArch64Disassembler *Dis = 1659 static_cast<const AArch64Disassembler *>(Decoder); 1660 1661 if (ShifterVal != 0 && ShifterVal != 1) 1662 return Fail; 1663 1664 if (Datasize) { 1665 if (Rd == 31 && !S) 1666 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1667 else 1668 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1669 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1670 } else { 1671 if (Rd == 31 && !S) 1672 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1673 else 1674 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1675 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1676 } 1677 1678 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1679 Inst.addOperand(MCOperand::createImm(ImmVal)); 1680 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1681 return Success; 1682 } 1683 1684 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1685 uint64_t Addr, 1686 const void *Decoder) { 1687 int64_t imm = fieldFromInstruction(insn, 0, 26); 1688 const AArch64Disassembler *Dis = 1689 static_cast<const AArch64Disassembler *>(Decoder); 1690 1691 // Sign-extend the 26-bit immediate. 1692 if (imm & (1 << (26 - 1))) 1693 imm |= ~((1LL << 26) - 1); 1694 1695 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1696 Inst.addOperand(MCOperand::createImm(imm)); 1697 1698 return Success; 1699 } 1700 1701 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1702 uint64_t Addr, 1703 const void *Decoder) { 1704 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1705 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1706 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1707 uint64_t pstate_field = (op1 << 3) | op2; 1708 1709 switch (pstate_field) { 1710 case 0x01: // XAFlag 1711 case 0x02: // AXFlag 1712 return Fail; 1713 } 1714 1715 if ((pstate_field == AArch64PState::PAN || 1716 pstate_field == AArch64PState::UAO || 1717 pstate_field == AArch64PState::SSBS) && crm > 1) 1718 return Fail; 1719 1720 Inst.addOperand(MCOperand::createImm(pstate_field)); 1721 Inst.addOperand(MCOperand::createImm(crm)); 1722 1723 const AArch64Disassembler *Dis = 1724 static_cast<const AArch64Disassembler *>(Decoder); 1725 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1726 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1727 return Success; 1728 return Fail; 1729 } 1730 1731 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1732 uint64_t Addr, const void *Decoder) { 1733 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1734 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1735 bit |= fieldFromInstruction(insn, 19, 5); 1736 int64_t dst = fieldFromInstruction(insn, 5, 14); 1737 const AArch64Disassembler *Dis = 1738 static_cast<const AArch64Disassembler *>(Decoder); 1739 1740 // Sign-extend 14-bit immediate. 1741 if (dst & (1 << (14 - 1))) 1742 dst |= ~((1LL << 14) - 1); 1743 1744 if (fieldFromInstruction(insn, 31, 1) == 0) 1745 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1746 else 1747 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1748 Inst.addOperand(MCOperand::createImm(bit)); 1749 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1750 Inst.addOperand(MCOperand::createImm(dst)); 1751 1752 return Success; 1753 } 1754 1755 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1756 unsigned RegClassID, 1757 unsigned RegNo, 1758 uint64_t Addr, 1759 const void *Decoder) { 1760 // Register number must be even (see CASP instruction) 1761 if (RegNo & 0x1) 1762 return Fail; 1763 1764 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1765 Inst.addOperand(MCOperand::createReg(Reg)); 1766 return Success; 1767 } 1768 1769 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1770 unsigned RegNo, 1771 uint64_t Addr, 1772 const void *Decoder) { 1773 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1774 AArch64::WSeqPairsClassRegClassID, 1775 RegNo, Addr, Decoder); 1776 } 1777 1778 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1779 unsigned RegNo, 1780 uint64_t Addr, 1781 const void *Decoder) { 1782 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1783 AArch64::XSeqPairsClassRegClassID, 1784 RegNo, Addr, Decoder); 1785 } 1786 1787 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 1788 uint64_t Addr, 1789 const void *Decoder) { 1790 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1791 unsigned imm = fieldFromInstruction(insn, 5, 13); 1792 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1793 return Fail; 1794 1795 // The same (tied) operand is added twice to the instruction. 1796 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1797 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1798 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1799 Inst.addOperand(MCOperand::createImm(imm)); 1800 return Success; 1801 } 1802 1803 template <int Bits> 1804 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1805 const void *Decoder) { 1806 if (Imm & ~((1LL << Bits) - 1)) 1807 return Fail; 1808 1809 // Imm is a signed immediate, so sign extend it. 1810 if (Imm & (1 << (Bits - 1))) 1811 Imm |= ~((1LL << Bits) - 1); 1812 1813 Inst.addOperand(MCOperand::createImm(Imm)); 1814 return Success; 1815 } 1816 1817 // Decode 8-bit signed/unsigned immediate for a given element width. 1818 template <int ElementWidth> 1819 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1820 uint64_t Addr, const void *Decoder) { 1821 unsigned Val = (uint8_t)Imm; 1822 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1823 if (ElementWidth == 8 && Shift) 1824 return Fail; 1825 Inst.addOperand(MCOperand::createImm(Val)); 1826 Inst.addOperand(MCOperand::createImm(Shift)); 1827 return Success; 1828 } 1829 1830 // Decode uimm4 ranged from 1-16. 1831 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1832 uint64_t Addr, const void *Decoder) { 1833 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1834 return Success; 1835 } 1836 1837 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1838 const void *Decoder) { 1839 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1840 Inst.addOperand(MCOperand::createImm(Imm)); 1841 return Success; 1842 } 1843 return Fail; 1844 } 1845