1 //===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating from LLVM IR into SelectionDAG IR. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 14 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 15 16 #include "StatepointLowering.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/MapVector.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/CodeGen/CodeGenCommonISel.h" 22 #include "llvm/CodeGen/ISDOpcodes.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/SwitchLoweringUtils.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/DebugLoc.h" 28 #include "llvm/IR/Instruction.h" 29 #include "llvm/Support/BranchProbability.h" 30 #include "llvm/Support/CodeGen.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include <algorithm> 34 #include <cassert> 35 #include <cstdint> 36 #include <utility> 37 #include <vector> 38 39 namespace llvm { 40 41 class AAResults; 42 class AllocaInst; 43 class AtomicCmpXchgInst; 44 class AtomicRMWInst; 45 class BasicBlock; 46 class BranchInst; 47 class CallInst; 48 class CallBrInst; 49 class CatchPadInst; 50 class CatchReturnInst; 51 class CatchSwitchInst; 52 class CleanupPadInst; 53 class CleanupReturnInst; 54 class Constant; 55 class ConstrainedFPIntrinsic; 56 class DbgValueInst; 57 class DataLayout; 58 class DIExpression; 59 class DILocalVariable; 60 class DILocation; 61 class FenceInst; 62 class FunctionLoweringInfo; 63 class GCFunctionInfo; 64 class GCRelocateInst; 65 class GCResultInst; 66 class GCStatepointInst; 67 class IndirectBrInst; 68 class InvokeInst; 69 class LandingPadInst; 70 class LLVMContext; 71 class LoadInst; 72 class MachineBasicBlock; 73 class PHINode; 74 class ResumeInst; 75 class ReturnInst; 76 class SDDbgValue; 77 class SelectionDAG; 78 class StoreInst; 79 class SwiftErrorValueTracking; 80 class SwitchInst; 81 class TargetLibraryInfo; 82 class TargetMachine; 83 class Type; 84 class VAArgInst; 85 class UnreachableInst; 86 class Use; 87 class User; 88 class Value; 89 90 //===----------------------------------------------------------------------===// 91 /// SelectionDAGBuilder - This is the common target-independent lowering 92 /// implementation that is parameterized by a TargetLowering object. 93 /// 94 class SelectionDAGBuilder { 95 /// The current instruction being visited. 96 const Instruction *CurInst = nullptr; 97 98 DenseMap<const Value*, SDValue> NodeMap; 99 100 /// Maps argument value for unused arguments. This is used 101 /// to preserve debug information for incoming arguments. 102 DenseMap<const Value*, SDValue> UnusedArgNodeMap; 103 104 /// Helper type for DanglingDebugInfoMap. 105 class DanglingDebugInfo { 106 const DbgValueInst* DI = nullptr; 107 DebugLoc dl; 108 unsigned SDNodeOrder = 0; 109 110 public: 111 DanglingDebugInfo() = default; 112 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) 113 : DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {} 114 115 const DbgValueInst* getDI() { return DI; } 116 DebugLoc getdl() { return dl; } 117 unsigned getSDNodeOrder() { return SDNodeOrder; } 118 }; 119 120 /// Helper type for DanglingDebugInfoMap. 121 typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector; 122 123 /// Keeps track of dbg_values for which we have not yet seen the referent. 124 /// We defer handling these until we do see it. 125 MapVector<const Value*, DanglingDebugInfoVector> DanglingDebugInfoMap; 126 127 public: 128 /// Loads are not emitted to the program immediately. We bunch them up and 129 /// then emit token factor nodes when possible. This allows us to get simple 130 /// disambiguation between loads without worrying about alias analysis. 131 SmallVector<SDValue, 8> PendingLoads; 132 133 /// State used while lowering a statepoint sequence (gc_statepoint, 134 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details. 135 StatepointLoweringState StatepointLowering; 136 137 private: 138 /// CopyToReg nodes that copy values to virtual registers for export to other 139 /// blocks need to be emitted before any terminator instruction, but they have 140 /// no other ordering requirements. We bunch them up and the emit a single 141 /// tokenfactor for them just before terminator instructions. 142 SmallVector<SDValue, 8> PendingExports; 143 144 /// Similar to loads, nodes corresponding to constrained FP intrinsics are 145 /// bunched up and emitted when necessary. These can be moved across each 146 /// other and any (normal) memory operation (load or store), but not across 147 /// calls or instructions having unspecified side effects. As a special 148 /// case, constrained FP intrinsics using fpexcept.strict may not be deleted 149 /// even if otherwise unused, so they need to be chained before any 150 /// terminator instruction (like PendingExports). We track the latter 151 /// set of nodes in a separate list. 152 SmallVector<SDValue, 8> PendingConstrainedFP; 153 SmallVector<SDValue, 8> PendingConstrainedFPStrict; 154 155 /// Update root to include all chains from the Pending list. 156 SDValue updateRoot(SmallVectorImpl<SDValue> &Pending); 157 158 /// A unique monotonically increasing number used to order the SDNodes we 159 /// create. 160 unsigned SDNodeOrder; 161 162 /// Determine the rank by weight of CC in [First,Last]. If CC has more weight 163 /// than each cluster in the range, its rank is 0. 164 unsigned caseClusterRank(const SwitchCG::CaseCluster &CC, 165 SwitchCG::CaseClusterIt First, 166 SwitchCG::CaseClusterIt Last); 167 168 /// Emit comparison and split W into two subtrees. 169 void splitWorkItem(SwitchCG::SwitchWorkList &WorkList, 170 const SwitchCG::SwitchWorkListItem &W, Value *Cond, 171 MachineBasicBlock *SwitchMBB); 172 173 /// Lower W. 174 void lowerWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond, 175 MachineBasicBlock *SwitchMBB, 176 MachineBasicBlock *DefaultMBB); 177 178 /// Peel the top probability case if it exceeds the threshold 179 MachineBasicBlock * 180 peelDominantCaseCluster(const SwitchInst &SI, 181 SwitchCG::CaseClusterVector &Clusters, 182 BranchProbability &PeeledCaseProb); 183 184 private: 185 const TargetMachine &TM; 186 187 public: 188 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling 189 /// nodes without a corresponding SDNode. 190 static const unsigned LowestSDNodeOrder = 1; 191 192 SelectionDAG &DAG; 193 const DataLayout *DL = nullptr; 194 AAResults *AA = nullptr; 195 const TargetLibraryInfo *LibInfo; 196 197 class SDAGSwitchLowering : public SwitchCG::SwitchLowering { 198 public: 199 SDAGSwitchLowering(SelectionDAGBuilder *sdb, FunctionLoweringInfo &funcinfo) 200 : SwitchCG::SwitchLowering(funcinfo), SDB(sdb) {} 201 202 virtual void addSuccessorWithProb( 203 MachineBasicBlock *Src, MachineBasicBlock *Dst, 204 BranchProbability Prob = BranchProbability::getUnknown()) override { 205 SDB->addSuccessorWithProb(Src, Dst, Prob); 206 } 207 208 private: 209 SelectionDAGBuilder *SDB; 210 }; 211 212 // Data related to deferred switch lowerings. Used to construct additional 213 // Basic Blocks in SelectionDAGISel::FinishBasicBlock. 214 std::unique_ptr<SDAGSwitchLowering> SL; 215 216 /// A StackProtectorDescriptor structure used to communicate stack protector 217 /// information in between SelectBasicBlock and FinishBasicBlock. 218 StackProtectorDescriptor SPDescriptor; 219 220 // Emit PHI-node-operand constants only once even if used by multiple 221 // PHI nodes. 222 DenseMap<const Constant *, unsigned> ConstantsOut; 223 224 /// Information about the function as a whole. 225 FunctionLoweringInfo &FuncInfo; 226 227 /// Information about the swifterror values used throughout the function. 228 SwiftErrorValueTracking &SwiftError; 229 230 /// Garbage collection metadata for the function. 231 GCFunctionInfo *GFI; 232 233 /// Map a landing pad to the call site indexes. 234 DenseMap<MachineBasicBlock *, SmallVector<unsigned, 4>> LPadToCallSiteMap; 235 236 /// This is set to true if a call in the current block has been translated as 237 /// a tail call. In this case, no subsequent DAG nodes should be created. 238 bool HasTailCall = false; 239 240 LLVMContext *Context; 241 242 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, 243 SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol) 244 : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag), 245 SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)), FuncInfo(funcinfo), 246 SwiftError(swifterror) {} 247 248 void init(GCFunctionInfo *gfi, AAResults *AA, 249 const TargetLibraryInfo *li); 250 251 /// Clear out the current SelectionDAG and the associated state and prepare 252 /// this SelectionDAGBuilder object to be used for a new block. This doesn't 253 /// clear out information about additional blocks that are needed to complete 254 /// switch lowering or PHI node updating; that information is cleared out as 255 /// it is consumed. 256 void clear(); 257 258 /// Clear the dangling debug information map. This function is separated from 259 /// the clear so that debug information that is dangling in a basic block can 260 /// be properly resolved in a different basic block. This allows the 261 /// SelectionDAG to resolve dangling debug information attached to PHI nodes. 262 void clearDanglingDebugInfo(); 263 264 /// Return the current virtual root of the Selection DAG, flushing any 265 /// PendingLoad items. This must be done before emitting a store or any other 266 /// memory node that may need to be ordered after any prior load instructions. 267 SDValue getMemoryRoot(); 268 269 /// Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) 270 /// items. This must be done before emitting any call other any other node 271 /// that may need to be ordered after FP instructions due to other side 272 /// effects. 273 SDValue getRoot(); 274 275 /// Similar to getRoot, but instead of flushing all the PendingLoad items, 276 /// flush all the PendingExports (and PendingConstrainedFPStrict) items. 277 /// It is necessary to do this before emitting a terminator instruction. 278 SDValue getControlRoot(); 279 280 SDLoc getCurSDLoc() const { 281 return SDLoc(CurInst, SDNodeOrder); 282 } 283 284 DebugLoc getCurDebugLoc() const { 285 return CurInst ? CurInst->getDebugLoc() : DebugLoc(); 286 } 287 288 void CopyValueToVirtualRegister(const Value *V, unsigned Reg); 289 290 void visit(const Instruction &I); 291 292 void visit(unsigned Opcode, const User &I); 293 294 /// If there was virtual register allocated for the value V emit CopyFromReg 295 /// of the specified type Ty. Return empty SDValue() otherwise. 296 SDValue getCopyFromRegs(const Value *V, Type *Ty); 297 298 /// Register a dbg_value which relies on a Value which we have not yet seen. 299 void addDanglingDebugInfo(const DbgValueInst *DI, DebugLoc DL, 300 unsigned Order); 301 302 /// If we have dangling debug info that describes \p Variable, or an 303 /// overlapping part of variable considering the \p Expr, then this method 304 /// will drop that debug info as it isn't valid any longer. 305 void dropDanglingDebugInfo(const DILocalVariable *Variable, 306 const DIExpression *Expr); 307 308 /// If we saw an earlier dbg_value referring to V, generate the debug data 309 /// structures now that we've seen its definition. 310 void resolveDanglingDebugInfo(const Value *V, SDValue Val); 311 312 /// For the given dangling debuginfo record, perform last-ditch efforts to 313 /// resolve the debuginfo to something that is represented in this DAG. If 314 /// this cannot be done, produce an Undef debug value record. 315 void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI); 316 317 /// For a given list of Values, attempt to create and record a SDDbgValue in 318 /// the SelectionDAG. 319 bool handleDebugValue(ArrayRef<const Value *> Values, DILocalVariable *Var, 320 DIExpression *Expr, DebugLoc CurDL, DebugLoc InstDL, 321 unsigned Order, bool IsVariadic); 322 323 /// Evict any dangling debug information, attempting to salvage it first. 324 void resolveOrClearDbgInfo(); 325 326 SDValue getValue(const Value *V); 327 328 SDValue getNonRegisterValue(const Value *V); 329 SDValue getValueImpl(const Value *V); 330 331 void setValue(const Value *V, SDValue NewN) { 332 SDValue &N = NodeMap[V]; 333 assert(!N.getNode() && "Already set a value for this node!"); 334 N = NewN; 335 } 336 337 void setUnusedArgValue(const Value *V, SDValue NewN) { 338 SDValue &N = UnusedArgNodeMap[V]; 339 assert(!N.getNode() && "Already set a value for this node!"); 340 N = NewN; 341 } 342 343 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, 344 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 345 MachineBasicBlock *SwitchBB, 346 Instruction::BinaryOps Opc, BranchProbability TProb, 347 BranchProbability FProb, bool InvertCond); 348 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, 349 MachineBasicBlock *FBB, 350 MachineBasicBlock *CurBB, 351 MachineBasicBlock *SwitchBB, 352 BranchProbability TProb, BranchProbability FProb, 353 bool InvertCond); 354 bool ShouldEmitAsBranches(const std::vector<SwitchCG::CaseBlock> &Cases); 355 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); 356 void CopyToExportRegsIfNeeded(const Value *V); 357 void ExportFromCurrentBlock(const Value *V); 358 void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, 359 bool IsMustTailCall, const BasicBlock *EHPadBB = nullptr); 360 361 // Lower range metadata from 0 to N to assert zext to an integer of nearest 362 // floor power of two. 363 SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, 364 SDValue Op); 365 366 void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, 367 const CallBase *Call, unsigned ArgIdx, 368 unsigned NumArgs, SDValue Callee, 369 Type *ReturnTy, bool IsPatchPoint); 370 371 std::pair<SDValue, SDValue> 372 lowerInvokable(TargetLowering::CallLoweringInfo &CLI, 373 const BasicBlock *EHPadBB = nullptr); 374 375 /// When an MBB was split during scheduling, update the 376 /// references that need to refer to the last resulting block. 377 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last); 378 379 /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes 380 /// of lowering into a STATEPOINT node. 381 struct StatepointLoweringInfo { 382 /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set 383 /// of gc pointers this STATEPOINT has to relocate. 384 SmallVector<const Value *, 16> Bases; 385 SmallVector<const Value *, 16> Ptrs; 386 387 /// The set of gc.relocate calls associated with this gc.statepoint. 388 SmallVector<const GCRelocateInst *, 16> GCRelocates; 389 390 /// The full list of gc arguments to the gc.statepoint being lowered. 391 ArrayRef<const Use> GCArgs; 392 393 /// The gc.statepoint instruction. 394 const Instruction *StatepointInstr = nullptr; 395 396 /// The list of gc transition arguments present in the gc.statepoint being 397 /// lowered. 398 ArrayRef<const Use> GCTransitionArgs; 399 400 /// The ID that the resulting STATEPOINT instruction has to report. 401 unsigned ID = -1; 402 403 /// Information regarding the underlying call instruction. 404 TargetLowering::CallLoweringInfo CLI; 405 406 /// The deoptimization state associated with this gc.statepoint call, if 407 /// any. 408 ArrayRef<const Use> DeoptState; 409 410 /// Flags associated with the meta arguments being lowered. 411 uint64_t StatepointFlags = -1; 412 413 /// The number of patchable bytes the call needs to get lowered into. 414 unsigned NumPatchBytes = -1; 415 416 /// The exception handling unwind destination, in case this represents an 417 /// invoke of gc.statepoint. 418 const BasicBlock *EHPadBB = nullptr; 419 420 explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {} 421 }; 422 423 /// Lower \p SLI into a STATEPOINT instruction. 424 SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI); 425 426 // This function is responsible for the whole statepoint lowering process. 427 // It uniformly handles invoke and call statepoints. 428 void LowerStatepoint(const GCStatepointInst &I, 429 const BasicBlock *EHPadBB = nullptr); 430 431 void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, 432 const BasicBlock *EHPadBB); 433 434 void LowerDeoptimizeCall(const CallInst *CI); 435 void LowerDeoptimizingReturn(); 436 437 void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee, 438 const BasicBlock *EHPadBB, 439 bool VarArgDisallowed, 440 bool ForceVoidReturnTy); 441 442 /// Returns the type of FrameIndex and TargetFrameIndex nodes. 443 MVT getFrameIndexTy() { 444 return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()); 445 } 446 447 private: 448 // Terminator instructions. 449 void visitRet(const ReturnInst &I); 450 void visitBr(const BranchInst &I); 451 void visitSwitch(const SwitchInst &I); 452 void visitIndirectBr(const IndirectBrInst &I); 453 void visitUnreachable(const UnreachableInst &I); 454 void visitCleanupRet(const CleanupReturnInst &I); 455 void visitCatchSwitch(const CatchSwitchInst &I); 456 void visitCatchRet(const CatchReturnInst &I); 457 void visitCatchPad(const CatchPadInst &I); 458 void visitCleanupPad(const CleanupPadInst &CPI); 459 460 BranchProbability getEdgeProbability(const MachineBasicBlock *Src, 461 const MachineBasicBlock *Dst) const; 462 void addSuccessorWithProb( 463 MachineBasicBlock *Src, MachineBasicBlock *Dst, 464 BranchProbability Prob = BranchProbability::getUnknown()); 465 466 public: 467 void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB); 468 void visitSPDescriptorParent(StackProtectorDescriptor &SPD, 469 MachineBasicBlock *ParentBB); 470 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD); 471 void visitBitTestHeader(SwitchCG::BitTestBlock &B, 472 MachineBasicBlock *SwitchBB); 473 void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, 474 BranchProbability BranchProbToNext, unsigned Reg, 475 SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB); 476 void visitJumpTable(SwitchCG::JumpTable &JT); 477 void visitJumpTableHeader(SwitchCG::JumpTable &JT, 478 SwitchCG::JumpTableHeader &JTH, 479 MachineBasicBlock *SwitchBB); 480 481 private: 482 // These all get lowered before this pass. 483 void visitInvoke(const InvokeInst &I); 484 void visitCallBr(const CallBrInst &I); 485 void visitResume(const ResumeInst &I); 486 487 void visitUnary(const User &I, unsigned Opcode); 488 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } 489 490 void visitBinary(const User &I, unsigned Opcode); 491 void visitShift(const User &I, unsigned Opcode); 492 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); } 493 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } 494 void visitSub(const User &I) { visitBinary(I, ISD::SUB); } 495 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); } 496 void visitMul(const User &I) { visitBinary(I, ISD::MUL); } 497 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } 498 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } 499 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } 500 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } 501 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } 502 void visitSDiv(const User &I); 503 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } 504 void visitAnd (const User &I) { visitBinary(I, ISD::AND); } 505 void visitOr (const User &I) { visitBinary(I, ISD::OR); } 506 void visitXor (const User &I) { visitBinary(I, ISD::XOR); } 507 void visitShl (const User &I) { visitShift(I, ISD::SHL); } 508 void visitLShr(const User &I) { visitShift(I, ISD::SRL); } 509 void visitAShr(const User &I) { visitShift(I, ISD::SRA); } 510 void visitICmp(const User &I); 511 void visitFCmp(const User &I); 512 // Visit the conversion instructions 513 void visitTrunc(const User &I); 514 void visitZExt(const User &I); 515 void visitSExt(const User &I); 516 void visitFPTrunc(const User &I); 517 void visitFPExt(const User &I); 518 void visitFPToUI(const User &I); 519 void visitFPToSI(const User &I); 520 void visitUIToFP(const User &I); 521 void visitSIToFP(const User &I); 522 void visitPtrToInt(const User &I); 523 void visitIntToPtr(const User &I); 524 void visitBitCast(const User &I); 525 void visitAddrSpaceCast(const User &I); 526 527 void visitExtractElement(const User &I); 528 void visitInsertElement(const User &I); 529 void visitShuffleVector(const User &I); 530 531 void visitExtractValue(const User &I); 532 void visitInsertValue(const User &I); 533 void visitLandingPad(const LandingPadInst &LP); 534 535 void visitGetElementPtr(const User &I); 536 void visitSelect(const User &I); 537 538 void visitAlloca(const AllocaInst &I); 539 void visitLoad(const LoadInst &I); 540 void visitStore(const StoreInst &I); 541 void visitMaskedLoad(const CallInst &I, bool IsExpanding = false); 542 void visitMaskedStore(const CallInst &I, bool IsCompressing = false); 543 void visitMaskedGather(const CallInst &I); 544 void visitMaskedScatter(const CallInst &I); 545 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I); 546 void visitAtomicRMW(const AtomicRMWInst &I); 547 void visitFence(const FenceInst &I); 548 void visitPHI(const PHINode &I); 549 void visitCall(const CallInst &I); 550 bool visitMemCmpBCmpCall(const CallInst &I); 551 bool visitMemPCpyCall(const CallInst &I); 552 bool visitMemChrCall(const CallInst &I); 553 bool visitStrCpyCall(const CallInst &I, bool isStpcpy); 554 bool visitStrCmpCall(const CallInst &I); 555 bool visitStrLenCall(const CallInst &I); 556 bool visitStrNLenCall(const CallInst &I); 557 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode); 558 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode); 559 void visitAtomicLoad(const LoadInst &I); 560 void visitAtomicStore(const StoreInst &I); 561 void visitLoadFromSwiftError(const LoadInst &I); 562 void visitStoreToSwiftError(const StoreInst &I); 563 void visitFreeze(const FreezeInst &I); 564 565 void visitInlineAsm(const CallBase &Call, 566 const BasicBlock *EHPadBB = nullptr); 567 void visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); 568 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); 569 void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI); 570 void visitVPLoadGather(const VPIntrinsic &VPIntrin, EVT VT, 571 SmallVector<SDValue, 7> &OpValues, bool isGather); 572 void visitVPStoreScatter(const VPIntrinsic &VPIntrin, 573 SmallVector<SDValue, 7> &OpValues, bool isScatter); 574 void visitVectorPredicationIntrinsic(const VPIntrinsic &VPIntrin); 575 576 void visitVAStart(const CallInst &I); 577 void visitVAArg(const VAArgInst &I); 578 void visitVAEnd(const CallInst &I); 579 void visitVACopy(const CallInst &I); 580 void visitStackmap(const CallInst &I); 581 void visitPatchpoint(const CallBase &CB, const BasicBlock *EHPadBB = nullptr); 582 583 // These two are implemented in StatepointLowering.cpp 584 void visitGCRelocate(const GCRelocateInst &Relocate); 585 void visitGCResult(const GCResultInst &I); 586 587 void visitVectorReduce(const CallInst &I, unsigned Intrinsic); 588 void visitVectorReverse(const CallInst &I); 589 void visitVectorSplice(const CallInst &I); 590 void visitStepVector(const CallInst &I); 591 592 void visitUserOp1(const Instruction &I) { 593 llvm_unreachable("UserOp1 should not exist at instruction selection time!"); 594 } 595 void visitUserOp2(const Instruction &I) { 596 llvm_unreachable("UserOp2 should not exist at instruction selection time!"); 597 } 598 599 void processIntegerCallValue(const Instruction &I, 600 SDValue Value, bool IsSigned); 601 602 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 603 604 void emitInlineAsmError(const CallBase &Call, const Twine &Message); 605 606 /// If V is an function argument then create corresponding DBG_VALUE machine 607 /// instruction for it now. At the end of instruction selection, they will be 608 /// inserted to the entry BB. 609 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable, 610 DIExpression *Expr, DILocation *DL, 611 bool IsDbgDeclare, const SDValue &N); 612 613 /// Return the next block after MBB, or nullptr if there is none. 614 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB); 615 616 /// Update the DAG and DAG builder with the relevant information after 617 /// a new root node has been created which could be a tail call. 618 void updateDAGForMaybeTailCall(SDValue MaybeTC); 619 620 /// Return the appropriate SDDbgValue based on N. 621 SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable, 622 DIExpression *Expr, const DebugLoc &dl, 623 unsigned DbgSDNodeOrder); 624 625 /// Lowers CallInst to an external symbol. 626 void lowerCallToExternalSymbol(const CallInst &I, const char *FunctionName); 627 628 SDValue lowerStartEH(SDValue Chain, const BasicBlock *EHPadBB, 629 MCSymbol *&BeginLabel); 630 SDValue lowerEndEH(SDValue Chain, const InvokeInst *II, 631 const BasicBlock *EHPadBB, MCSymbol *BeginLabel); 632 }; 633 634 /// This struct represents the registers (physical or virtual) 635 /// that a particular set of values is assigned, and the type information about 636 /// the value. The most common situation is to represent one value at a time, 637 /// but struct or array values are handled element-wise as multiple values. The 638 /// splitting of aggregates is performed recursively, so that we never have 639 /// aggregate-typed registers. The values at this point do not necessarily have 640 /// legal types, so each value may require one or more registers of some legal 641 /// type. 642 /// 643 struct RegsForValue { 644 /// The value types of the values, which may not be legal, and 645 /// may need be promoted or synthesized from one or more registers. 646 SmallVector<EVT, 4> ValueVTs; 647 648 /// The value types of the registers. This is the same size as ValueVTs and it 649 /// records, for each value, what the type of the assigned register or 650 /// registers are. (Individual values are never synthesized from more than one 651 /// type of register.) 652 /// 653 /// With virtual registers, the contents of RegVTs is redundant with TLI's 654 /// getRegisterType member function, however when with physical registers 655 /// it is necessary to have a separate record of the types. 656 SmallVector<MVT, 4> RegVTs; 657 658 /// This list holds the registers assigned to the values. 659 /// Each legal or promoted value requires one register, and each 660 /// expanded value requires multiple registers. 661 SmallVector<unsigned, 4> Regs; 662 663 /// This list holds the number of registers for each value. 664 SmallVector<unsigned, 4> RegCount; 665 666 /// Records if this value needs to be treated in an ABI dependant manner, 667 /// different to normal type legalization. 668 Optional<CallingConv::ID> CallConv; 669 670 RegsForValue() = default; 671 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt, 672 Optional<CallingConv::ID> CC = None); 673 RegsForValue(LLVMContext &Context, const TargetLowering &TLI, 674 const DataLayout &DL, unsigned Reg, Type *Ty, 675 Optional<CallingConv::ID> CC); 676 677 bool isABIMangled() const { 678 return CallConv.hasValue(); 679 } 680 681 /// Add the specified values to this one. 682 void append(const RegsForValue &RHS) { 683 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 684 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 685 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 686 RegCount.push_back(RHS.Regs.size()); 687 } 688 689 /// Emit a series of CopyFromReg nodes that copies from this value and returns 690 /// the result as a ValueVTs value. This uses Chain/Flag as the input and 691 /// updates them for the output Chain/Flag. If the Flag pointer is NULL, no 692 /// flag is used. 693 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 694 const SDLoc &dl, SDValue &Chain, SDValue *Flag, 695 const Value *V = nullptr) const; 696 697 /// Emit a series of CopyToReg nodes that copies the specified value into the 698 /// registers specified by this object. This uses Chain/Flag as the input and 699 /// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no 700 /// flag is used. If V is not nullptr, then it is used in printing better 701 /// diagnostic messages on error. 702 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, 703 SDValue &Chain, SDValue *Flag, const Value *V = nullptr, 704 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const; 705 706 /// Add this value to the specified inlineasm node operand list. This adds the 707 /// code marker, matching input operand index (if applicable), and includes 708 /// the number of values added into it. 709 void AddInlineAsmOperands(unsigned Code, bool HasMatching, 710 unsigned MatchingIdx, const SDLoc &dl, 711 SelectionDAG &DAG, std::vector<SDValue> &Ops) const; 712 713 /// Check if the total RegCount is greater than one. 714 bool occupiesMultipleRegs() const { 715 return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1; 716 } 717 718 /// Return a list of registers and their sizes. 719 SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const; 720 }; 721 722 } // end namespace llvm 723 724 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 725