18bcb0991SDimitry Andric //=- MachineLoopUtils.cpp - Functions for manipulating loops ----------------=//
28bcb0991SDimitry Andric //
38bcb0991SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
48bcb0991SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
58bcb0991SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
68bcb0991SDimitry Andric //
78bcb0991SDimitry Andric //===----------------------------------------------------------------------===//
88bcb0991SDimitry Andric
98bcb0991SDimitry Andric #include "llvm/CodeGen/MachineLoopUtils.h"
108bcb0991SDimitry Andric #include "llvm/CodeGen/MachineBasicBlock.h"
118bcb0991SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
128bcb0991SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
138bcb0991SDimitry Andric using namespace llvm;
148bcb0991SDimitry Andric
158bcb0991SDimitry Andric namespace {
168bcb0991SDimitry Andric // MI's parent and BB are clones of each other. Find the equivalent copy of MI
178bcb0991SDimitry Andric // in BB.
findEquivalentInstruction(MachineInstr & MI,MachineBasicBlock * BB)188bcb0991SDimitry Andric MachineInstr &findEquivalentInstruction(MachineInstr &MI,
198bcb0991SDimitry Andric MachineBasicBlock *BB) {
208bcb0991SDimitry Andric MachineBasicBlock *PB = MI.getParent();
218bcb0991SDimitry Andric unsigned Offset = std::distance(PB->instr_begin(), MachineBasicBlock::instr_iterator(MI));
228bcb0991SDimitry Andric return *std::next(BB->instr_begin(), Offset);
238bcb0991SDimitry Andric }
248bcb0991SDimitry Andric } // namespace
258bcb0991SDimitry Andric
PeelSingleBlockLoop(LoopPeelDirection Direction,MachineBasicBlock * Loop,MachineRegisterInfo & MRI,const TargetInstrInfo * TII)268bcb0991SDimitry Andric MachineBasicBlock *llvm::PeelSingleBlockLoop(LoopPeelDirection Direction,
278bcb0991SDimitry Andric MachineBasicBlock *Loop,
288bcb0991SDimitry Andric MachineRegisterInfo &MRI,
298bcb0991SDimitry Andric const TargetInstrInfo *TII) {
308bcb0991SDimitry Andric MachineFunction &MF = *Loop->getParent();
318bcb0991SDimitry Andric MachineBasicBlock *Preheader = *Loop->pred_begin();
328bcb0991SDimitry Andric if (Preheader == Loop)
338bcb0991SDimitry Andric Preheader = *std::next(Loop->pred_begin());
348bcb0991SDimitry Andric MachineBasicBlock *Exit = *Loop->succ_begin();
358bcb0991SDimitry Andric if (Exit == Loop)
368bcb0991SDimitry Andric Exit = *std::next(Loop->succ_begin());
378bcb0991SDimitry Andric
388bcb0991SDimitry Andric MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(Loop->getBasicBlock());
398bcb0991SDimitry Andric if (Direction == LPD_Front)
408bcb0991SDimitry Andric MF.insert(Loop->getIterator(), NewBB);
418bcb0991SDimitry Andric else
428bcb0991SDimitry Andric MF.insert(std::next(Loop->getIterator()), NewBB);
438bcb0991SDimitry Andric
445ffd83dbSDimitry Andric DenseMap<Register, Register> Remaps;
458bcb0991SDimitry Andric auto InsertPt = NewBB->end();
468bcb0991SDimitry Andric for (MachineInstr &MI : *Loop) {
478bcb0991SDimitry Andric MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
488bcb0991SDimitry Andric NewBB->insert(InsertPt, NewMI);
498bcb0991SDimitry Andric for (MachineOperand &MO : NewMI->defs()) {
508bcb0991SDimitry Andric Register OrigR = MO.getReg();
518bcb0991SDimitry Andric if (OrigR.isPhysical())
528bcb0991SDimitry Andric continue;
538bcb0991SDimitry Andric Register &R = Remaps[OrigR];
548bcb0991SDimitry Andric R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
558bcb0991SDimitry Andric MO.setReg(R);
568bcb0991SDimitry Andric
578bcb0991SDimitry Andric if (Direction == LPD_Back) {
588bcb0991SDimitry Andric // Replace all uses outside the original loop with the new register.
598bcb0991SDimitry Andric // FIXME: is the use_iterator stable enough to mutate register uses
608bcb0991SDimitry Andric // while iterating?
618bcb0991SDimitry Andric SmallVector<MachineOperand *, 4> Uses;
628bcb0991SDimitry Andric for (auto &Use : MRI.use_operands(OrigR))
638bcb0991SDimitry Andric if (Use.getParent()->getParent() != Loop)
648bcb0991SDimitry Andric Uses.push_back(&Use);
658bcb0991SDimitry Andric for (auto *Use : Uses) {
66*81ad6265SDimitry Andric const TargetRegisterClass *ConstrainRegClass =
678bcb0991SDimitry Andric MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
68*81ad6265SDimitry Andric assert(ConstrainRegClass &&
69*81ad6265SDimitry Andric "Expected a valid constrained register class!");
70*81ad6265SDimitry Andric (void)ConstrainRegClass;
718bcb0991SDimitry Andric Use->setReg(R);
728bcb0991SDimitry Andric }
738bcb0991SDimitry Andric }
748bcb0991SDimitry Andric }
758bcb0991SDimitry Andric }
768bcb0991SDimitry Andric
778bcb0991SDimitry Andric for (auto I = NewBB->getFirstNonPHI(); I != NewBB->end(); ++I)
788bcb0991SDimitry Andric for (MachineOperand &MO : I->uses())
798bcb0991SDimitry Andric if (MO.isReg() && Remaps.count(MO.getReg()))
808bcb0991SDimitry Andric MO.setReg(Remaps[MO.getReg()]);
818bcb0991SDimitry Andric
828bcb0991SDimitry Andric for (auto I = NewBB->begin(); I->isPHI(); ++I) {
838bcb0991SDimitry Andric MachineInstr &MI = *I;
848bcb0991SDimitry Andric unsigned LoopRegIdx = 3, InitRegIdx = 1;
858bcb0991SDimitry Andric if (MI.getOperand(2).getMBB() != Preheader)
868bcb0991SDimitry Andric std::swap(LoopRegIdx, InitRegIdx);
878bcb0991SDimitry Andric MachineInstr &OrigPhi = findEquivalentInstruction(MI, Loop);
888bcb0991SDimitry Andric assert(OrigPhi.isPHI());
898bcb0991SDimitry Andric if (Direction == LPD_Front) {
908bcb0991SDimitry Andric // When peeling front, we are only left with the initial value from the
918bcb0991SDimitry Andric // preheader.
928bcb0991SDimitry Andric Register R = MI.getOperand(LoopRegIdx).getReg();
938bcb0991SDimitry Andric if (Remaps.count(R))
948bcb0991SDimitry Andric R = Remaps[R];
958bcb0991SDimitry Andric OrigPhi.getOperand(InitRegIdx).setReg(R);
96*81ad6265SDimitry Andric MI.removeOperand(LoopRegIdx + 1);
97*81ad6265SDimitry Andric MI.removeOperand(LoopRegIdx + 0);
988bcb0991SDimitry Andric } else {
998bcb0991SDimitry Andric // When peeling back, the initial value is the loop-carried value from
1008bcb0991SDimitry Andric // the original loop.
1018bcb0991SDimitry Andric Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
1028bcb0991SDimitry Andric MI.getOperand(LoopRegIdx).setReg(LoopReg);
103*81ad6265SDimitry Andric MI.removeOperand(InitRegIdx + 1);
104*81ad6265SDimitry Andric MI.removeOperand(InitRegIdx + 0);
1058bcb0991SDimitry Andric }
1068bcb0991SDimitry Andric }
1078bcb0991SDimitry Andric
1088bcb0991SDimitry Andric DebugLoc DL;
1098bcb0991SDimitry Andric if (Direction == LPD_Front) {
110*81ad6265SDimitry Andric Preheader->ReplaceUsesOfBlockWith(Loop, NewBB);
1118bcb0991SDimitry Andric NewBB->addSuccessor(Loop);
1128bcb0991SDimitry Andric Loop->replacePhiUsesWith(Preheader, NewBB);
113*81ad6265SDimitry Andric Preheader->updateTerminator(Loop);
1148bcb0991SDimitry Andric TII->removeBranch(*NewBB);
1158bcb0991SDimitry Andric TII->insertBranch(*NewBB, Loop, nullptr, {}, DL);
1168bcb0991SDimitry Andric } else {
1178bcb0991SDimitry Andric Loop->replaceSuccessor(Exit, NewBB);
1188bcb0991SDimitry Andric Exit->replacePhiUsesWith(Loop, NewBB);
1198bcb0991SDimitry Andric NewBB->addSuccessor(Exit);
1208bcb0991SDimitry Andric
1218bcb0991SDimitry Andric MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1228bcb0991SDimitry Andric SmallVector<MachineOperand, 4> Cond;
1238bcb0991SDimitry Andric bool CanAnalyzeBr = !TII->analyzeBranch(*Loop, TBB, FBB, Cond);
1248bcb0991SDimitry Andric (void)CanAnalyzeBr;
1258bcb0991SDimitry Andric assert(CanAnalyzeBr && "Must be able to analyze the loop branch!");
1268bcb0991SDimitry Andric TII->removeBranch(*Loop);
1278bcb0991SDimitry Andric TII->insertBranch(*Loop, TBB == Exit ? NewBB : TBB,
1288bcb0991SDimitry Andric FBB == Exit ? NewBB : FBB, Cond, DL);
1298bcb0991SDimitry Andric if (TII->removeBranch(*NewBB) > 0)
1308bcb0991SDimitry Andric TII->insertBranch(*NewBB, Exit, nullptr, {}, DL);
1318bcb0991SDimitry Andric }
1328bcb0991SDimitry Andric
1338bcb0991SDimitry Andric return NewBB;
1348bcb0991SDimitry Andric }
135