1bdd1243dSDimitry Andric //===-- TargetParser - Parser for target features ---------------*- C++ -*-===// 2bdd1243dSDimitry Andric // 3bdd1243dSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4bdd1243dSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5bdd1243dSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6bdd1243dSDimitry Andric // 7bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 8bdd1243dSDimitry Andric // 9bdd1243dSDimitry Andric // This file implements a target parser to recognise hardware features such as 10bdd1243dSDimitry Andric // FPU/CPU/ARCH names as well as specific support such as HDIV, etc. 11bdd1243dSDimitry Andric // 12bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 13bdd1243dSDimitry Andric 14bdd1243dSDimitry Andric #ifndef LLVM_TARGETPARSER_TARGETPARSER_H 15bdd1243dSDimitry Andric #define LLVM_TARGETPARSER_TARGETPARSER_H 16bdd1243dSDimitry Andric 1706c3fb27SDimitry Andric #include "llvm/ADT/StringMap.h" 18bdd1243dSDimitry Andric #include "llvm/ADT/StringRef.h" 19bdd1243dSDimitry Andric 20bdd1243dSDimitry Andric namespace llvm { 21bdd1243dSDimitry Andric 22bdd1243dSDimitry Andric template <typename T> class SmallVectorImpl; 23bdd1243dSDimitry Andric class Triple; 24bdd1243dSDimitry Andric 25bdd1243dSDimitry Andric // Target specific information in their own namespaces. 26bdd1243dSDimitry Andric // (ARM/AArch64/X86 are declared in ARM/AArch64/X86TargetParser.h) 27bdd1243dSDimitry Andric // These should be generated from TableGen because the information is already 28bdd1243dSDimitry Andric // there, and there is where new information about targets will be added. 29bdd1243dSDimitry Andric // FIXME: To TableGen this we need to make some table generated files available 30bdd1243dSDimitry Andric // even if the back-end is not compiled with LLVM, plus we need to create a new 31bdd1243dSDimitry Andric // back-end to TableGen to create these clean tables. 32bdd1243dSDimitry Andric namespace AMDGPU { 33bdd1243dSDimitry Andric 34bdd1243dSDimitry Andric /// GPU kinds supported by the AMDGPU target. 35bdd1243dSDimitry Andric enum GPUKind : uint32_t { 36bdd1243dSDimitry Andric // Not specified processor. 37bdd1243dSDimitry Andric GK_NONE = 0, 38bdd1243dSDimitry Andric 39bdd1243dSDimitry Andric // R600-based processors. 40bdd1243dSDimitry Andric GK_R600 = 1, 41bdd1243dSDimitry Andric GK_R630 = 2, 42bdd1243dSDimitry Andric GK_RS880 = 3, 43bdd1243dSDimitry Andric GK_RV670 = 4, 44bdd1243dSDimitry Andric GK_RV710 = 5, 45bdd1243dSDimitry Andric GK_RV730 = 6, 46bdd1243dSDimitry Andric GK_RV770 = 7, 47bdd1243dSDimitry Andric GK_CEDAR = 8, 48bdd1243dSDimitry Andric GK_CYPRESS = 9, 49bdd1243dSDimitry Andric GK_JUNIPER = 10, 50bdd1243dSDimitry Andric GK_REDWOOD = 11, 51bdd1243dSDimitry Andric GK_SUMO = 12, 52bdd1243dSDimitry Andric GK_BARTS = 13, 53bdd1243dSDimitry Andric GK_CAICOS = 14, 54bdd1243dSDimitry Andric GK_CAYMAN = 15, 55bdd1243dSDimitry Andric GK_TURKS = 16, 56bdd1243dSDimitry Andric 57bdd1243dSDimitry Andric GK_R600_FIRST = GK_R600, 58bdd1243dSDimitry Andric GK_R600_LAST = GK_TURKS, 59bdd1243dSDimitry Andric 60bdd1243dSDimitry Andric // AMDGCN-based processors. 61bdd1243dSDimitry Andric GK_GFX600 = 32, 62bdd1243dSDimitry Andric GK_GFX601 = 33, 63bdd1243dSDimitry Andric GK_GFX602 = 34, 64bdd1243dSDimitry Andric 65bdd1243dSDimitry Andric GK_GFX700 = 40, 66bdd1243dSDimitry Andric GK_GFX701 = 41, 67bdd1243dSDimitry Andric GK_GFX702 = 42, 68bdd1243dSDimitry Andric GK_GFX703 = 43, 69bdd1243dSDimitry Andric GK_GFX704 = 44, 70bdd1243dSDimitry Andric GK_GFX705 = 45, 71bdd1243dSDimitry Andric 72bdd1243dSDimitry Andric GK_GFX801 = 50, 73bdd1243dSDimitry Andric GK_GFX802 = 51, 74bdd1243dSDimitry Andric GK_GFX803 = 52, 75bdd1243dSDimitry Andric GK_GFX805 = 53, 76bdd1243dSDimitry Andric GK_GFX810 = 54, 77bdd1243dSDimitry Andric 78bdd1243dSDimitry Andric GK_GFX900 = 60, 79bdd1243dSDimitry Andric GK_GFX902 = 61, 80bdd1243dSDimitry Andric GK_GFX904 = 62, 81bdd1243dSDimitry Andric GK_GFX906 = 63, 82bdd1243dSDimitry Andric GK_GFX908 = 64, 83bdd1243dSDimitry Andric GK_GFX909 = 65, 84bdd1243dSDimitry Andric GK_GFX90A = 66, 85bdd1243dSDimitry Andric GK_GFX90C = 67, 86bdd1243dSDimitry Andric GK_GFX940 = 68, 8706c3fb27SDimitry Andric GK_GFX941 = 69, 8806c3fb27SDimitry Andric GK_GFX942 = 70, 89bdd1243dSDimitry Andric 90bdd1243dSDimitry Andric GK_GFX1010 = 71, 91bdd1243dSDimitry Andric GK_GFX1011 = 72, 92bdd1243dSDimitry Andric GK_GFX1012 = 73, 93bdd1243dSDimitry Andric GK_GFX1013 = 74, 94bdd1243dSDimitry Andric GK_GFX1030 = 75, 95bdd1243dSDimitry Andric GK_GFX1031 = 76, 96bdd1243dSDimitry Andric GK_GFX1032 = 77, 97bdd1243dSDimitry Andric GK_GFX1033 = 78, 98bdd1243dSDimitry Andric GK_GFX1034 = 79, 99bdd1243dSDimitry Andric GK_GFX1035 = 80, 100bdd1243dSDimitry Andric GK_GFX1036 = 81, 101bdd1243dSDimitry Andric 102bdd1243dSDimitry Andric GK_GFX1100 = 90, 103bdd1243dSDimitry Andric GK_GFX1101 = 91, 104bdd1243dSDimitry Andric GK_GFX1102 = 92, 105bdd1243dSDimitry Andric GK_GFX1103 = 93, 10606c3fb27SDimitry Andric GK_GFX1150 = 94, 10706c3fb27SDimitry Andric GK_GFX1151 = 95, 108*0fca6ea1SDimitry Andric GK_GFX1152 = 96, 109bdd1243dSDimitry Andric 1105f757f3fSDimitry Andric GK_GFX1200 = 100, 1115f757f3fSDimitry Andric GK_GFX1201 = 101, 1125f757f3fSDimitry Andric 113bdd1243dSDimitry Andric GK_AMDGCN_FIRST = GK_GFX600, 1145f757f3fSDimitry Andric GK_AMDGCN_LAST = GK_GFX1201, 115*0fca6ea1SDimitry Andric 116*0fca6ea1SDimitry Andric GK_GFX9_GENERIC = 192, 117*0fca6ea1SDimitry Andric GK_GFX10_1_GENERIC = 193, 118*0fca6ea1SDimitry Andric GK_GFX10_3_GENERIC = 194, 119*0fca6ea1SDimitry Andric GK_GFX11_GENERIC = 195, 120*0fca6ea1SDimitry Andric GK_GFX12_GENERIC = 196, 121*0fca6ea1SDimitry Andric 122*0fca6ea1SDimitry Andric GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC, 123*0fca6ea1SDimitry Andric GK_AMDGCN_GENERIC_LAST = GK_GFX12_GENERIC, 124bdd1243dSDimitry Andric }; 125bdd1243dSDimitry Andric 126bdd1243dSDimitry Andric /// Instruction set architecture version. 127bdd1243dSDimitry Andric struct IsaVersion { 128bdd1243dSDimitry Andric unsigned Major; 129bdd1243dSDimitry Andric unsigned Minor; 130bdd1243dSDimitry Andric unsigned Stepping; 131bdd1243dSDimitry Andric }; 132bdd1243dSDimitry Andric 133bdd1243dSDimitry Andric // This isn't comprehensive for now, just things that are needed from the 134bdd1243dSDimitry Andric // frontend driver. 135bdd1243dSDimitry Andric enum ArchFeatureKind : uint32_t { 136bdd1243dSDimitry Andric FEATURE_NONE = 0, 137bdd1243dSDimitry Andric 138bdd1243dSDimitry Andric // These features only exist for r600, and are implied true for amdgcn. 139bdd1243dSDimitry Andric FEATURE_FMA = 1 << 1, 140bdd1243dSDimitry Andric FEATURE_LDEXP = 1 << 2, 141bdd1243dSDimitry Andric FEATURE_FP64 = 1 << 3, 142bdd1243dSDimitry Andric 143bdd1243dSDimitry Andric // Common features. 144bdd1243dSDimitry Andric FEATURE_FAST_FMA_F32 = 1 << 4, 145bdd1243dSDimitry Andric FEATURE_FAST_DENORMAL_F32 = 1 << 5, 146bdd1243dSDimitry Andric 147bdd1243dSDimitry Andric // Wavefront 32 is available. 148bdd1243dSDimitry Andric FEATURE_WAVE32 = 1 << 6, 149bdd1243dSDimitry Andric 150bdd1243dSDimitry Andric // Xnack is available. 151bdd1243dSDimitry Andric FEATURE_XNACK = 1 << 7, 152bdd1243dSDimitry Andric 153bdd1243dSDimitry Andric // Sram-ecc is available. 154bdd1243dSDimitry Andric FEATURE_SRAMECC = 1 << 8, 15506c3fb27SDimitry Andric 15606c3fb27SDimitry Andric // WGP mode is supported. 15706c3fb27SDimitry Andric FEATURE_WGP = 1 << 9, 158bdd1243dSDimitry Andric }; 159bdd1243dSDimitry Andric 160*0fca6ea1SDimitry Andric enum FeatureError : uint32_t { 161*0fca6ea1SDimitry Andric NO_ERROR = 0, 162*0fca6ea1SDimitry Andric INVALID_FEATURE_COMBINATION, 163*0fca6ea1SDimitry Andric UNSUPPORTED_TARGET_FEATURE 164*0fca6ea1SDimitry Andric }; 165*0fca6ea1SDimitry Andric 166*0fca6ea1SDimitry Andric StringRef getArchFamilyNameAMDGCN(GPUKind AK); 167*0fca6ea1SDimitry Andric 168bdd1243dSDimitry Andric StringRef getArchNameAMDGCN(GPUKind AK); 169bdd1243dSDimitry Andric StringRef getArchNameR600(GPUKind AK); 170bdd1243dSDimitry Andric StringRef getCanonicalArchName(const Triple &T, StringRef Arch); 171bdd1243dSDimitry Andric GPUKind parseArchAMDGCN(StringRef CPU); 172bdd1243dSDimitry Andric GPUKind parseArchR600(StringRef CPU); 173bdd1243dSDimitry Andric unsigned getArchAttrAMDGCN(GPUKind AK); 174bdd1243dSDimitry Andric unsigned getArchAttrR600(GPUKind AK); 175bdd1243dSDimitry Andric 176bdd1243dSDimitry Andric void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values); 177bdd1243dSDimitry Andric void fillValidArchListR600(SmallVectorImpl<StringRef> &Values); 178bdd1243dSDimitry Andric 179bdd1243dSDimitry Andric IsaVersion getIsaVersion(StringRef GPU); 180bdd1243dSDimitry Andric 18106c3fb27SDimitry Andric /// Fills Features map with default values for given target GPU 18206c3fb27SDimitry Andric void fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, 18306c3fb27SDimitry Andric StringMap<bool> &Features); 18406c3fb27SDimitry Andric 18506c3fb27SDimitry Andric /// Inserts wave size feature for given GPU into features map 186*0fca6ea1SDimitry Andric std::pair<FeatureError, StringRef> 187*0fca6ea1SDimitry Andric insertWaveSizeFeature(StringRef GPU, const Triple &T, 188*0fca6ea1SDimitry Andric StringMap<bool> &Features); 18906c3fb27SDimitry Andric 190bdd1243dSDimitry Andric } // namespace AMDGPU 191bdd1243dSDimitry Andric } // namespace llvm 192bdd1243dSDimitry Andric 193bdd1243dSDimitry Andric #endif 194