1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110 HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Wraps a machine instruction to add patchability constraints. An 174/// instruction wrapped in PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the instruction, the 177/// second operand is an immediate denoting the opcode of the original 178/// instruction. The rest of the operands are the operands of the 179/// original instruction. 180HANDLE_TARGET_OPCODE(PATCHABLE_OP) 181 182/// This is a marker instruction which gets translated into a nop sled, useful 183/// for inserting instrumentation instructions at runtime. 184HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 185 186/// Wraps a return instruction and its operands to enable adding nop sleds 187/// either before or after the return. The nop sleds are useful for inserting 188/// instrumentation instructions at runtime. 189/// The patch here replaces the return instruction. 190HANDLE_TARGET_OPCODE(PATCHABLE_RET) 191 192/// This is a marker instruction which gets translated into a nop sled, useful 193/// for inserting instrumentation instructions at runtime. 194/// The patch here prepends the return instruction. 195/// The same thing as in x86_64 is not possible for ARM because it has multiple 196/// return instructions. Furthermore, CPU allows parametrized and even 197/// conditional return instructions. In the current ARM implementation we are 198/// making use of the fact that currently LLVM doesn't seem to generate 199/// conditional return instructions. 200/// On ARM, the same instruction can be used for popping multiple registers 201/// from the stack and returning (it just pops pc register too), and LLVM 202/// generates it sometimes. So we can't insert the sled between this stack 203/// adjustment and the return without splitting the original instruction into 2 204/// instructions. So on ARM, rather than jumping into the exit trampoline, we 205/// call it, it does the tracing, preserves the stack and returns. 206HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 207 208/// Wraps a tail call instruction and its operands to enable adding nop sleds 209/// either before or after the tail exit. We use this as a disambiguation from 210/// PATCHABLE_RET which specifically only works for return instructions. 211HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 212 213/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 214/// be patched to insert instrumentation instructions. 215HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 216 217/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 218/// can be patched to insert instrumentation instructions. 219HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 220 221HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 222 223/// The following generic opcodes are not supposed to appear after ISel. 224/// This is something we might want to relax, but for now, this is convenient 225/// to produce diagnostics. 226 227/// Instructions which should not exist past instruction selection, but do not 228/// generate code. These instructions only act as optimization hints. 229HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 230HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 231HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 232HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 233 G_ASSERT_SEXT) 234HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 235 G_ASSERT_ALIGN) 236 237/// Generic ADD instruction. This is an integer add. 238HANDLE_TARGET_OPCODE(G_ADD) 239HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 240 241/// Generic SUB instruction. This is an integer sub. 242HANDLE_TARGET_OPCODE(G_SUB) 243 244// Generic multiply instruction. 245HANDLE_TARGET_OPCODE(G_MUL) 246 247// Generic signed division instruction. 248HANDLE_TARGET_OPCODE(G_SDIV) 249 250// Generic unsigned division instruction. 251HANDLE_TARGET_OPCODE(G_UDIV) 252 253// Generic signed remainder instruction. 254HANDLE_TARGET_OPCODE(G_SREM) 255 256// Generic unsigned remainder instruction. 257HANDLE_TARGET_OPCODE(G_UREM) 258 259// Generic signed divrem instruction. 260HANDLE_TARGET_OPCODE(G_SDIVREM) 261 262// Generic unsigned divrem instruction. 263HANDLE_TARGET_OPCODE(G_UDIVREM) 264 265/// Generic bitwise and instruction. 266HANDLE_TARGET_OPCODE(G_AND) 267 268/// Generic bitwise or instruction. 269HANDLE_TARGET_OPCODE(G_OR) 270 271/// Generic bitwise exclusive-or instruction. 272HANDLE_TARGET_OPCODE(G_XOR) 273 274 275HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 276 277/// Generic PHI instruction with types. 278HANDLE_TARGET_OPCODE(G_PHI) 279 280/// Generic instruction to materialize the address of an alloca or other 281/// stack-based object. 282HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 283 284/// Generic reference to global value. 285HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 286 287/// Generic instruction to extract blocks of bits from the register given 288/// (typically a sub-register COPY after instruction selection). 289HANDLE_TARGET_OPCODE(G_EXTRACT) 290 291HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 292 293/// Generic instruction to insert blocks of bits from the registers given into 294/// the source. 295HANDLE_TARGET_OPCODE(G_INSERT) 296 297/// Generic instruction to paste a variable number of components together into a 298/// larger register. 299HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 300 301/// Generic instruction to create a vector value from a number of scalar 302/// components. 303HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 304 305/// Generic instruction to create a vector value from a number of scalar 306/// components, which have types larger than the result vector elt type. 307HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 308 309/// Generic instruction to create a vector by concatenating multiple vectors. 310HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 311 312/// Generic pointer to int conversion. 313HANDLE_TARGET_OPCODE(G_PTRTOINT) 314 315/// Generic int to pointer conversion. 316HANDLE_TARGET_OPCODE(G_INTTOPTR) 317 318/// Generic bitcast. The source and destination types must be different, or a 319/// COPY is the relevant instruction. 320HANDLE_TARGET_OPCODE(G_BITCAST) 321 322/// Generic freeze. 323HANDLE_TARGET_OPCODE(G_FREEZE) 324 325/// INTRINSIC trunc intrinsic. 326HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 327 328/// INTRINSIC round intrinsic. 329HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 330 331/// INTRINSIC round to integer intrinsic. 332HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 333 334/// INTRINSIC roundeven intrinsic. 335HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 336 337/// INTRINSIC readcyclecounter 338HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 339 340/// Generic load (including anyext load) 341HANDLE_TARGET_OPCODE(G_LOAD) 342 343/// Generic signext load 344HANDLE_TARGET_OPCODE(G_SEXTLOAD) 345 346/// Generic zeroext load 347HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 348 349/// Generic indexed load (including anyext load) 350HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 351 352/// Generic indexed signext load 353HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 354 355/// Generic indexed zeroext load 356HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 357 358/// Generic store. 359HANDLE_TARGET_OPCODE(G_STORE) 360 361/// Generic indexed store. 362HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 363 364/// Generic atomic cmpxchg with internal success check. 365HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 366 367/// Generic atomic cmpxchg. 368HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 369 370/// Generic atomicrmw. 371HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 372HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 373HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 374HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 375HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 376HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 377HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 378HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 379HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 380HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 381HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 382HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 383HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 384 385// Generic atomic fence 386HANDLE_TARGET_OPCODE(G_FENCE) 387 388/// Generic conditional branch instruction. 389HANDLE_TARGET_OPCODE(G_BRCOND) 390 391/// Generic indirect branch instruction. 392HANDLE_TARGET_OPCODE(G_BRINDIRECT) 393 394/// Generic intrinsic use (without side effects). 395HANDLE_TARGET_OPCODE(G_INTRINSIC) 396 397/// Generic intrinsic use (with side effects). 398HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 399 400/// Generic extension allowing rubbish in high bits. 401HANDLE_TARGET_OPCODE(G_ANYEXT) 402 403/// Generic instruction to discard the high bits of a register. This differs 404/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 405/// each element individually, G_EXTRACT will typically discard the high 406/// elements of the vector. 407HANDLE_TARGET_OPCODE(G_TRUNC) 408 409/// Generic integer constant. 410HANDLE_TARGET_OPCODE(G_CONSTANT) 411 412/// Generic floating constant. 413HANDLE_TARGET_OPCODE(G_FCONSTANT) 414 415/// Generic va_start instruction. Stores to its one pointer operand. 416HANDLE_TARGET_OPCODE(G_VASTART) 417 418/// Generic va_start instruction. Stores to its one pointer operand. 419HANDLE_TARGET_OPCODE(G_VAARG) 420 421// Generic sign extend 422HANDLE_TARGET_OPCODE(G_SEXT) 423HANDLE_TARGET_OPCODE(G_SEXT_INREG) 424 425// Generic zero extend 426HANDLE_TARGET_OPCODE(G_ZEXT) 427 428// Generic left-shift 429HANDLE_TARGET_OPCODE(G_SHL) 430 431// Generic logical right-shift 432HANDLE_TARGET_OPCODE(G_LSHR) 433 434// Generic arithmetic right-shift 435HANDLE_TARGET_OPCODE(G_ASHR) 436 437// Generic funnel left shift 438HANDLE_TARGET_OPCODE(G_FSHL) 439 440// Generic funnel right shift 441HANDLE_TARGET_OPCODE(G_FSHR) 442 443// Generic right rotate 444HANDLE_TARGET_OPCODE(G_ROTR) 445 446// Generic left rotate 447HANDLE_TARGET_OPCODE(G_ROTL) 448 449/// Generic integer-base comparison, also applicable to vectors of integers. 450HANDLE_TARGET_OPCODE(G_ICMP) 451 452/// Generic floating-point comparison, also applicable to vectors. 453HANDLE_TARGET_OPCODE(G_FCMP) 454 455/// Generic select. 456HANDLE_TARGET_OPCODE(G_SELECT) 457 458/// Generic unsigned add instruction, consuming the normal operands and 459/// producing the result and a carry flag. 460HANDLE_TARGET_OPCODE(G_UADDO) 461 462/// Generic unsigned add instruction, consuming the normal operands plus a carry 463/// flag, and similarly producing the result and a carry flag. 464HANDLE_TARGET_OPCODE(G_UADDE) 465 466/// Generic unsigned sub instruction, consuming the normal operands and 467/// producing the result and a carry flag. 468HANDLE_TARGET_OPCODE(G_USUBO) 469 470/// Generic unsigned subtract instruction, consuming the normal operands plus a 471/// carry flag, and similarly producing the result and a carry flag. 472HANDLE_TARGET_OPCODE(G_USUBE) 473 474/// Generic signed add instruction, producing the result and a signed overflow 475/// flag. 476HANDLE_TARGET_OPCODE(G_SADDO) 477 478/// Generic signed add instruction, consuming the normal operands plus a carry 479/// flag, and similarly producing the result and a carry flag. 480HANDLE_TARGET_OPCODE(G_SADDE) 481 482/// Generic signed subtract instruction, producing the result and a signed 483/// overflow flag. 484HANDLE_TARGET_OPCODE(G_SSUBO) 485 486/// Generic signed sub instruction, consuming the normal operands plus a carry 487/// flag, and similarly producing the result and a carry flag. 488HANDLE_TARGET_OPCODE(G_SSUBE) 489 490/// Generic unsigned multiply instruction, producing the result and a signed 491/// overflow flag. 492HANDLE_TARGET_OPCODE(G_UMULO) 493 494/// Generic signed multiply instruction, producing the result and a signed 495/// overflow flag. 496HANDLE_TARGET_OPCODE(G_SMULO) 497 498// Multiply two numbers at twice the incoming bit width (unsigned) and return 499// the high half of the result. 500HANDLE_TARGET_OPCODE(G_UMULH) 501 502// Multiply two numbers at twice the incoming bit width (signed) and return 503// the high half of the result. 504HANDLE_TARGET_OPCODE(G_SMULH) 505 506/// Generic saturating unsigned addition. 507HANDLE_TARGET_OPCODE(G_UADDSAT) 508 509/// Generic saturating signed addition. 510HANDLE_TARGET_OPCODE(G_SADDSAT) 511 512/// Generic saturating unsigned subtraction. 513HANDLE_TARGET_OPCODE(G_USUBSAT) 514 515/// Generic saturating signed subtraction. 516HANDLE_TARGET_OPCODE(G_SSUBSAT) 517 518/// Generic saturating unsigned left shift. 519HANDLE_TARGET_OPCODE(G_USHLSAT) 520 521/// Generic saturating signed left shift. 522HANDLE_TARGET_OPCODE(G_SSHLSAT) 523 524// Perform signed fixed point multiplication 525HANDLE_TARGET_OPCODE(G_SMULFIX) 526 527// Perform unsigned fixed point multiplication 528HANDLE_TARGET_OPCODE(G_UMULFIX) 529 530// Perform signed, saturating fixed point multiplication 531HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 532 533// Perform unsigned, saturating fixed point multiplication 534HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 535 536// Perform signed fixed point division 537HANDLE_TARGET_OPCODE(G_SDIVFIX) 538 539// Perform unsigned fixed point division 540HANDLE_TARGET_OPCODE(G_UDIVFIX) 541 542// Perform signed, saturating fixed point division 543HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 544 545// Perform unsigned, saturating fixed point division 546HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 547 548/// Generic FP addition. 549HANDLE_TARGET_OPCODE(G_FADD) 550 551/// Generic FP subtraction. 552HANDLE_TARGET_OPCODE(G_FSUB) 553 554/// Generic FP multiplication. 555HANDLE_TARGET_OPCODE(G_FMUL) 556 557/// Generic FMA multiplication. Behaves like llvm fma intrinsic 558HANDLE_TARGET_OPCODE(G_FMA) 559 560/// Generic FP multiply and add. Behaves as separate fmul and fadd. 561HANDLE_TARGET_OPCODE(G_FMAD) 562 563/// Generic FP division. 564HANDLE_TARGET_OPCODE(G_FDIV) 565 566/// Generic FP remainder. 567HANDLE_TARGET_OPCODE(G_FREM) 568 569/// Generic FP exponentiation. 570HANDLE_TARGET_OPCODE(G_FPOW) 571 572/// Generic FP exponentiation, with an integer exponent. 573HANDLE_TARGET_OPCODE(G_FPOWI) 574 575/// Generic base-e exponential of a value. 576HANDLE_TARGET_OPCODE(G_FEXP) 577 578/// Generic base-2 exponential of a value. 579HANDLE_TARGET_OPCODE(G_FEXP2) 580 581/// Floating point base-e logarithm of a value. 582HANDLE_TARGET_OPCODE(G_FLOG) 583 584/// Floating point base-2 logarithm of a value. 585HANDLE_TARGET_OPCODE(G_FLOG2) 586 587/// Floating point base-10 logarithm of a value. 588HANDLE_TARGET_OPCODE(G_FLOG10) 589 590/// Generic FP negation. 591HANDLE_TARGET_OPCODE(G_FNEG) 592 593/// Generic FP extension. 594HANDLE_TARGET_OPCODE(G_FPEXT) 595 596/// Generic float to signed-int conversion 597HANDLE_TARGET_OPCODE(G_FPTRUNC) 598 599/// Generic float to signed-int conversion 600HANDLE_TARGET_OPCODE(G_FPTOSI) 601 602/// Generic float to unsigned-int conversion 603HANDLE_TARGET_OPCODE(G_FPTOUI) 604 605/// Generic signed-int to float conversion 606HANDLE_TARGET_OPCODE(G_SITOFP) 607 608/// Generic unsigned-int to float conversion 609HANDLE_TARGET_OPCODE(G_UITOFP) 610 611/// Generic FP absolute value. 612HANDLE_TARGET_OPCODE(G_FABS) 613 614/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 615/// not require that X and Y have the same type, just that they are both 616/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 617/// f64) is allowed. 618HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 619 620/// Generic FP canonicalize value. 621HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 622 623/// FP min/max matching libm's fmin/fmax 624HANDLE_TARGET_OPCODE(G_FMINNUM) 625HANDLE_TARGET_OPCODE(G_FMAXNUM) 626 627/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 628HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 629HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 630 631/// FP min/max matching IEEE-754 2018 draft semantics. 632HANDLE_TARGET_OPCODE(G_FMINIMUM) 633HANDLE_TARGET_OPCODE(G_FMAXIMUM) 634 635/// Generic pointer offset 636HANDLE_TARGET_OPCODE(G_PTR_ADD) 637 638/// Clear the specified bits in a pointer. 639HANDLE_TARGET_OPCODE(G_PTRMASK) 640 641/// Generic signed integer minimum. 642HANDLE_TARGET_OPCODE(G_SMIN) 643 644/// Generic signed integer maximum. 645HANDLE_TARGET_OPCODE(G_SMAX) 646 647/// Generic unsigned integer maximum. 648HANDLE_TARGET_OPCODE(G_UMIN) 649 650/// Generic unsigned integer maximum. 651HANDLE_TARGET_OPCODE(G_UMAX) 652 653/// Generic integer absolute value. 654HANDLE_TARGET_OPCODE(G_ABS) 655 656HANDLE_TARGET_OPCODE(G_LROUND) 657HANDLE_TARGET_OPCODE(G_LLROUND) 658 659/// Generic BRANCH instruction. This is an unconditional branch. 660HANDLE_TARGET_OPCODE(G_BR) 661 662/// Generic branch to jump table entry. 663HANDLE_TARGET_OPCODE(G_BRJT) 664 665/// Generic insertelement. 666HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 667 668/// Generic extractelement. 669HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 670 671/// Generic shufflevector. 672HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 673 674/// Generic count trailing zeroes. 675HANDLE_TARGET_OPCODE(G_CTTZ) 676 677/// Same as above, undefined for zero inputs. 678HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 679 680/// Generic count leading zeroes. 681HANDLE_TARGET_OPCODE(G_CTLZ) 682 683/// Same as above, undefined for zero inputs. 684HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 685 686/// Generic count bits. 687HANDLE_TARGET_OPCODE(G_CTPOP) 688 689/// Generic byte swap. 690HANDLE_TARGET_OPCODE(G_BSWAP) 691 692/// Generic bit reverse. 693HANDLE_TARGET_OPCODE(G_BITREVERSE) 694 695/// Floating point ceil. 696HANDLE_TARGET_OPCODE(G_FCEIL) 697 698/// Floating point cosine. 699HANDLE_TARGET_OPCODE(G_FCOS) 700 701/// Floating point sine. 702HANDLE_TARGET_OPCODE(G_FSIN) 703 704/// Floating point square root. 705HANDLE_TARGET_OPCODE(G_FSQRT) 706 707/// Floating point floor. 708HANDLE_TARGET_OPCODE(G_FFLOOR) 709 710/// Floating point round to next integer. 711HANDLE_TARGET_OPCODE(G_FRINT) 712 713/// Floating point round to nearest integer. 714HANDLE_TARGET_OPCODE(G_FNEARBYINT) 715 716/// Generic AddressSpaceCast. 717HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 718 719/// Generic block address 720HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 721 722/// Generic jump table address 723HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 724 725/// Generic dynamic stack allocation. 726HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 727 728/// Strict floating point instructions. 729HANDLE_TARGET_OPCODE(G_STRICT_FADD) 730HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 731HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 732HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 733HANDLE_TARGET_OPCODE(G_STRICT_FREM) 734HANDLE_TARGET_OPCODE(G_STRICT_FMA) 735HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 736 737/// read_register intrinsic 738HANDLE_TARGET_OPCODE(G_READ_REGISTER) 739 740/// write_register intrinsic 741HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 742 743/// llvm.memcpy intrinsic 744HANDLE_TARGET_OPCODE(G_MEMCPY) 745 746/// llvm.memcpy.inline intrinsic 747HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 748 749/// llvm.memmove intrinsic 750HANDLE_TARGET_OPCODE(G_MEMMOVE) 751 752/// llvm.memset intrinsic 753HANDLE_TARGET_OPCODE(G_MEMSET) 754HANDLE_TARGET_OPCODE(G_BZERO) 755 756/// Vector reductions 757HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 758HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 759HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 760HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 761HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 762HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 763HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 764HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 765HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 766HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 767HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 768HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 769HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 770HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 771HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 772 773HANDLE_TARGET_OPCODE(G_SBFX) 774HANDLE_TARGET_OPCODE(G_UBFX) 775 776/// Marker for the end of the generic opcode. 777/// This is used to check if an opcode is in the range of the 778/// generic opcodes. 779HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 780 781/// BUILTIN_OP_END - This must be the last enum value in this list. 782/// The target-specific post-isel opcode values start here. 783HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 784