1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Wraps a machine instruction to add patchability constraints. An 174/// instruction wrapped in PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the instruction, the 177/// second operand is an immediate denoting the opcode of the original 178/// instruction. The rest of the operands are the operands of the 179/// original instruction. 180/// PATCHABLE_OP can be used as second operand to only insert a nop of 181/// required size. 182HANDLE_TARGET_OPCODE(PATCHABLE_OP) 183 184/// This is a marker instruction which gets translated into a nop sled, useful 185/// for inserting instrumentation instructions at runtime. 186HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 187 188/// Wraps a return instruction and its operands to enable adding nop sleds 189/// either before or after the return. The nop sleds are useful for inserting 190/// instrumentation instructions at runtime. 191/// The patch here replaces the return instruction. 192HANDLE_TARGET_OPCODE(PATCHABLE_RET) 193 194/// This is a marker instruction which gets translated into a nop sled, useful 195/// for inserting instrumentation instructions at runtime. 196/// The patch here prepends the return instruction. 197/// The same thing as in x86_64 is not possible for ARM because it has multiple 198/// return instructions. Furthermore, CPU allows parametrized and even 199/// conditional return instructions. In the current ARM implementation we are 200/// making use of the fact that currently LLVM doesn't seem to generate 201/// conditional return instructions. 202/// On ARM, the same instruction can be used for popping multiple registers 203/// from the stack and returning (it just pops pc register too), and LLVM 204/// generates it sometimes. So we can't insert the sled between this stack 205/// adjustment and the return without splitting the original instruction into 2 206/// instructions. So on ARM, rather than jumping into the exit trampoline, we 207/// call it, it does the tracing, preserves the stack and returns. 208HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 209 210/// Wraps a tail call instruction and its operands to enable adding nop sleds 211/// either before or after the tail exit. We use this as a disambiguation from 212/// PATCHABLE_RET which specifically only works for return instructions. 213HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 214 215/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 216/// be patched to insert instrumentation instructions. 217HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 218 219/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 220/// can be patched to insert instrumentation instructions. 221HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 222 223HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 224 225// This is a fence with the singlethread scope. It represents a compiler memory 226// barrier, but does not correspond to any generated instruction. 227HANDLE_TARGET_OPCODE(MEMBARRIER) 228 229// Provides information about what jump table the following indirect branch is 230// using. 231HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO) 232 233/// The following generic opcodes are not supposed to appear after ISel. 234/// This is something we might want to relax, but for now, this is convenient 235/// to produce diagnostics. 236 237/// Instructions which should not exist past instruction selection, but do not 238/// generate code. These instructions only act as optimization hints. 239HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 240HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 241HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 242HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 243 G_ASSERT_SEXT) 244HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 245 G_ASSERT_ALIGN) 246 247/// Generic ADD instruction. This is an integer add. 248HANDLE_TARGET_OPCODE(G_ADD) 249HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 250 251/// Generic SUB instruction. This is an integer sub. 252HANDLE_TARGET_OPCODE(G_SUB) 253 254// Generic multiply instruction. 255HANDLE_TARGET_OPCODE(G_MUL) 256 257// Generic signed division instruction. 258HANDLE_TARGET_OPCODE(G_SDIV) 259 260// Generic unsigned division instruction. 261HANDLE_TARGET_OPCODE(G_UDIV) 262 263// Generic signed remainder instruction. 264HANDLE_TARGET_OPCODE(G_SREM) 265 266// Generic unsigned remainder instruction. 267HANDLE_TARGET_OPCODE(G_UREM) 268 269// Generic signed divrem instruction. 270HANDLE_TARGET_OPCODE(G_SDIVREM) 271 272// Generic unsigned divrem instruction. 273HANDLE_TARGET_OPCODE(G_UDIVREM) 274 275/// Generic bitwise and instruction. 276HANDLE_TARGET_OPCODE(G_AND) 277 278/// Generic bitwise or instruction. 279HANDLE_TARGET_OPCODE(G_OR) 280 281/// Generic bitwise exclusive-or instruction. 282HANDLE_TARGET_OPCODE(G_XOR) 283 284 285HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 286 287/// Generic PHI instruction with types. 288HANDLE_TARGET_OPCODE(G_PHI) 289 290/// Generic instruction to materialize the address of an alloca or other 291/// stack-based object. 292HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 293 294/// Generic reference to global value. 295HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 296 297/// Generic instruction to materialize the address of an object in the constant 298/// pool. 299HANDLE_TARGET_OPCODE(G_CONSTANT_POOL) 300 301/// Generic instruction to extract blocks of bits from the register given 302/// (typically a sub-register COPY after instruction selection). 303HANDLE_TARGET_OPCODE(G_EXTRACT) 304 305HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 306 307/// Generic instruction to insert blocks of bits from the registers given into 308/// the source. 309HANDLE_TARGET_OPCODE(G_INSERT) 310 311/// Generic instruction to paste a variable number of components together into a 312/// larger register. 313HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 314 315/// Generic instruction to create a vector value from a number of scalar 316/// components. 317HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 318 319/// Generic instruction to create a vector value from a number of scalar 320/// components, which have types larger than the result vector elt type. 321HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 322 323/// Generic instruction to create a vector by concatenating multiple vectors. 324HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 325 326/// Generic pointer to int conversion. 327HANDLE_TARGET_OPCODE(G_PTRTOINT) 328 329/// Generic int to pointer conversion. 330HANDLE_TARGET_OPCODE(G_INTTOPTR) 331 332/// Generic bitcast. The source and destination types must be different, or a 333/// COPY is the relevant instruction. 334HANDLE_TARGET_OPCODE(G_BITCAST) 335 336/// Generic freeze. 337HANDLE_TARGET_OPCODE(G_FREEZE) 338 339/// Constant folding barrier. 340HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER) 341 342// INTRINSIC fptrunc_round intrinsic. 343HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 344 345/// INTRINSIC trunc intrinsic. 346HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 347 348/// INTRINSIC round intrinsic. 349HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 350 351/// INTRINSIC round to integer intrinsic. 352HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 353 354/// INTRINSIC roundeven intrinsic. 355HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 356 357/// INTRINSIC readcyclecounter 358HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 359 360/// Generic load (including anyext load) 361HANDLE_TARGET_OPCODE(G_LOAD) 362 363/// Generic signext load 364HANDLE_TARGET_OPCODE(G_SEXTLOAD) 365 366/// Generic zeroext load 367HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 368 369/// Generic indexed load (including anyext load) 370HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 371 372/// Generic indexed signext load 373HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 374 375/// Generic indexed zeroext load 376HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 377 378/// Generic store. 379HANDLE_TARGET_OPCODE(G_STORE) 380 381/// Generic indexed store. 382HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 383 384/// Generic atomic cmpxchg with internal success check. 385HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 386 387/// Generic atomic cmpxchg. 388HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 389 390/// Generic atomicrmw. 391HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 392HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 393HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 394HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 395HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 396HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 397HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 398HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 399HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 400HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 401HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 402HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 403HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 404HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 405HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 406HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) 407HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) 408 409// Marker for start of Generic AtomicRMW opcodes 410HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) 411 412// Marker for end of Generic AtomicRMW opcodes 413HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP) 414 415// Generic atomic fence 416HANDLE_TARGET_OPCODE(G_FENCE) 417 418/// Generic prefetch 419HANDLE_TARGET_OPCODE(G_PREFETCH) 420 421/// Generic conditional branch instruction. 422HANDLE_TARGET_OPCODE(G_BRCOND) 423 424/// Generic indirect branch instruction. 425HANDLE_TARGET_OPCODE(G_BRINDIRECT) 426 427/// Begin an invoke region marker. 428HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) 429 430/// Generic intrinsic use (without side effects). 431HANDLE_TARGET_OPCODE(G_INTRINSIC) 432 433/// Generic intrinsic use (with side effects). 434HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 435 436/// Generic intrinsic use (without side effects). 437HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT) 438 439/// Generic intrinsic use (with side effects). 440HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) 441 442/// Generic extension allowing rubbish in high bits. 443HANDLE_TARGET_OPCODE(G_ANYEXT) 444 445/// Generic instruction to discard the high bits of a register. This differs 446/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 447/// each element individually, G_EXTRACT will typically discard the high 448/// elements of the vector. 449HANDLE_TARGET_OPCODE(G_TRUNC) 450 451/// Generic integer constant. 452HANDLE_TARGET_OPCODE(G_CONSTANT) 453 454/// Generic floating constant. 455HANDLE_TARGET_OPCODE(G_FCONSTANT) 456 457/// Generic va_start instruction. Stores to its one pointer operand. 458HANDLE_TARGET_OPCODE(G_VASTART) 459 460/// Generic va_arg instruction. Stores to its one pointer operand. 461HANDLE_TARGET_OPCODE(G_VAARG) 462 463// Generic sign extend 464HANDLE_TARGET_OPCODE(G_SEXT) 465HANDLE_TARGET_OPCODE(G_SEXT_INREG) 466 467// Generic zero extend 468HANDLE_TARGET_OPCODE(G_ZEXT) 469 470// Generic left-shift 471HANDLE_TARGET_OPCODE(G_SHL) 472 473// Generic logical right-shift 474HANDLE_TARGET_OPCODE(G_LSHR) 475 476// Generic arithmetic right-shift 477HANDLE_TARGET_OPCODE(G_ASHR) 478 479// Generic funnel left shift 480HANDLE_TARGET_OPCODE(G_FSHL) 481 482// Generic funnel right shift 483HANDLE_TARGET_OPCODE(G_FSHR) 484 485// Generic right rotate 486HANDLE_TARGET_OPCODE(G_ROTR) 487 488// Generic left rotate 489HANDLE_TARGET_OPCODE(G_ROTL) 490 491/// Generic integer-base comparison, also applicable to vectors of integers. 492HANDLE_TARGET_OPCODE(G_ICMP) 493 494/// Generic floating-point comparison, also applicable to vectors. 495HANDLE_TARGET_OPCODE(G_FCMP) 496 497/// Generic select. 498HANDLE_TARGET_OPCODE(G_SELECT) 499 500/// Generic unsigned add instruction, consuming the normal operands and 501/// producing the result and a carry flag. 502HANDLE_TARGET_OPCODE(G_UADDO) 503 504/// Generic unsigned add instruction, consuming the normal operands plus a carry 505/// flag, and similarly producing the result and a carry flag. 506HANDLE_TARGET_OPCODE(G_UADDE) 507 508/// Generic unsigned sub instruction, consuming the normal operands and 509/// producing the result and a carry flag. 510HANDLE_TARGET_OPCODE(G_USUBO) 511 512/// Generic unsigned subtract instruction, consuming the normal operands plus a 513/// carry flag, and similarly producing the result and a carry flag. 514HANDLE_TARGET_OPCODE(G_USUBE) 515 516/// Generic signed add instruction, producing the result and a signed overflow 517/// flag. 518HANDLE_TARGET_OPCODE(G_SADDO) 519 520/// Generic signed add instruction, consuming the normal operands plus a carry 521/// flag, and similarly producing the result and a carry flag. 522HANDLE_TARGET_OPCODE(G_SADDE) 523 524/// Generic signed subtract instruction, producing the result and a signed 525/// overflow flag. 526HANDLE_TARGET_OPCODE(G_SSUBO) 527 528/// Generic signed sub instruction, consuming the normal operands plus a carry 529/// flag, and similarly producing the result and a carry flag. 530HANDLE_TARGET_OPCODE(G_SSUBE) 531 532/// Generic unsigned multiply instruction, producing the result and a signed 533/// overflow flag. 534HANDLE_TARGET_OPCODE(G_UMULO) 535 536/// Generic signed multiply instruction, producing the result and a signed 537/// overflow flag. 538HANDLE_TARGET_OPCODE(G_SMULO) 539 540// Multiply two numbers at twice the incoming bit width (unsigned) and return 541// the high half of the result. 542HANDLE_TARGET_OPCODE(G_UMULH) 543 544// Multiply two numbers at twice the incoming bit width (signed) and return 545// the high half of the result. 546HANDLE_TARGET_OPCODE(G_SMULH) 547 548/// Generic saturating unsigned addition. 549HANDLE_TARGET_OPCODE(G_UADDSAT) 550 551/// Generic saturating signed addition. 552HANDLE_TARGET_OPCODE(G_SADDSAT) 553 554/// Generic saturating unsigned subtraction. 555HANDLE_TARGET_OPCODE(G_USUBSAT) 556 557/// Generic saturating signed subtraction. 558HANDLE_TARGET_OPCODE(G_SSUBSAT) 559 560/// Generic saturating unsigned left shift. 561HANDLE_TARGET_OPCODE(G_USHLSAT) 562 563/// Generic saturating signed left shift. 564HANDLE_TARGET_OPCODE(G_SSHLSAT) 565 566// Perform signed fixed point multiplication 567HANDLE_TARGET_OPCODE(G_SMULFIX) 568 569// Perform unsigned fixed point multiplication 570HANDLE_TARGET_OPCODE(G_UMULFIX) 571 572// Perform signed, saturating fixed point multiplication 573HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 574 575// Perform unsigned, saturating fixed point multiplication 576HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 577 578// Perform signed fixed point division 579HANDLE_TARGET_OPCODE(G_SDIVFIX) 580 581// Perform unsigned fixed point division 582HANDLE_TARGET_OPCODE(G_UDIVFIX) 583 584// Perform signed, saturating fixed point division 585HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 586 587// Perform unsigned, saturating fixed point division 588HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 589 590/// Generic FP addition. 591HANDLE_TARGET_OPCODE(G_FADD) 592 593/// Generic FP subtraction. 594HANDLE_TARGET_OPCODE(G_FSUB) 595 596/// Generic FP multiplication. 597HANDLE_TARGET_OPCODE(G_FMUL) 598 599/// Generic FMA multiplication. Behaves like llvm fma intrinsic 600HANDLE_TARGET_OPCODE(G_FMA) 601 602/// Generic FP multiply and add. Behaves as separate fmul and fadd. 603HANDLE_TARGET_OPCODE(G_FMAD) 604 605/// Generic FP division. 606HANDLE_TARGET_OPCODE(G_FDIV) 607 608/// Generic FP remainder. 609HANDLE_TARGET_OPCODE(G_FREM) 610 611/// Generic FP exponentiation. 612HANDLE_TARGET_OPCODE(G_FPOW) 613 614/// Generic FP exponentiation, with an integer exponent. 615HANDLE_TARGET_OPCODE(G_FPOWI) 616 617/// Generic base-e exponential of a value. 618HANDLE_TARGET_OPCODE(G_FEXP) 619 620/// Generic base-2 exponential of a value. 621HANDLE_TARGET_OPCODE(G_FEXP2) 622 623/// Generic base-10 exponential of a value. 624HANDLE_TARGET_OPCODE(G_FEXP10) 625 626/// Floating point base-e logarithm of a value. 627HANDLE_TARGET_OPCODE(G_FLOG) 628 629/// Floating point base-2 logarithm of a value. 630HANDLE_TARGET_OPCODE(G_FLOG2) 631 632/// Floating point base-10 logarithm of a value. 633HANDLE_TARGET_OPCODE(G_FLOG10) 634 635/// Floating point x * 2^n 636HANDLE_TARGET_OPCODE(G_FLDEXP) 637 638/// Floating point extract fraction and exponent. 639HANDLE_TARGET_OPCODE(G_FFREXP) 640 641/// Generic FP negation. 642HANDLE_TARGET_OPCODE(G_FNEG) 643 644/// Generic FP extension. 645HANDLE_TARGET_OPCODE(G_FPEXT) 646 647/// Generic float to signed-int conversion 648HANDLE_TARGET_OPCODE(G_FPTRUNC) 649 650/// Generic float to signed-int conversion 651HANDLE_TARGET_OPCODE(G_FPTOSI) 652 653/// Generic float to unsigned-int conversion 654HANDLE_TARGET_OPCODE(G_FPTOUI) 655 656/// Generic signed-int to float conversion 657HANDLE_TARGET_OPCODE(G_SITOFP) 658 659/// Generic unsigned-int to float conversion 660HANDLE_TARGET_OPCODE(G_UITOFP) 661 662/// Generic FP absolute value. 663HANDLE_TARGET_OPCODE(G_FABS) 664 665/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 666/// not require that X and Y have the same type, just that they are both 667/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 668/// f64) is allowed. 669HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 670 671/// Generic test for floating-point class. 672HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 673 674/// Generic FP canonicalize value. 675HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 676 677/// FP min/max matching libm's fmin/fmax 678HANDLE_TARGET_OPCODE(G_FMINNUM) 679HANDLE_TARGET_OPCODE(G_FMAXNUM) 680 681/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 682HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 683HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 684 685/// FP min/max matching IEEE-754 2018 draft semantics. 686HANDLE_TARGET_OPCODE(G_FMINIMUM) 687HANDLE_TARGET_OPCODE(G_FMAXIMUM) 688 689/// Access to FP environment. 690HANDLE_TARGET_OPCODE(G_GET_FPENV) 691HANDLE_TARGET_OPCODE(G_SET_FPENV) 692HANDLE_TARGET_OPCODE(G_RESET_FPENV) 693HANDLE_TARGET_OPCODE(G_GET_FPMODE) 694HANDLE_TARGET_OPCODE(G_SET_FPMODE) 695HANDLE_TARGET_OPCODE(G_RESET_FPMODE) 696 697/// Generic pointer offset 698HANDLE_TARGET_OPCODE(G_PTR_ADD) 699 700/// Clear the specified bits in a pointer. 701HANDLE_TARGET_OPCODE(G_PTRMASK) 702 703/// Generic signed integer minimum. 704HANDLE_TARGET_OPCODE(G_SMIN) 705 706/// Generic signed integer maximum. 707HANDLE_TARGET_OPCODE(G_SMAX) 708 709/// Generic unsigned integer maximum. 710HANDLE_TARGET_OPCODE(G_UMIN) 711 712/// Generic unsigned integer maximum. 713HANDLE_TARGET_OPCODE(G_UMAX) 714 715/// Generic integer absolute value. 716HANDLE_TARGET_OPCODE(G_ABS) 717 718HANDLE_TARGET_OPCODE(G_LROUND) 719HANDLE_TARGET_OPCODE(G_LLROUND) 720 721/// Generic BRANCH instruction. This is an unconditional branch. 722HANDLE_TARGET_OPCODE(G_BR) 723 724/// Generic branch to jump table entry. 725HANDLE_TARGET_OPCODE(G_BRJT) 726 727/// Generic insertelement. 728HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 729 730/// Generic extractelement. 731HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 732 733/// Generic shufflevector. 734HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 735 736/// Generic count trailing zeroes. 737HANDLE_TARGET_OPCODE(G_CTTZ) 738 739/// Same as above, undefined for zero inputs. 740HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 741 742/// Generic count leading zeroes. 743HANDLE_TARGET_OPCODE(G_CTLZ) 744 745/// Same as above, undefined for zero inputs. 746HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 747 748/// Generic count bits. 749HANDLE_TARGET_OPCODE(G_CTPOP) 750 751/// Generic byte swap. 752HANDLE_TARGET_OPCODE(G_BSWAP) 753 754/// Generic bit reverse. 755HANDLE_TARGET_OPCODE(G_BITREVERSE) 756 757/// Floating point ceil. 758HANDLE_TARGET_OPCODE(G_FCEIL) 759 760/// Floating point cosine. 761HANDLE_TARGET_OPCODE(G_FCOS) 762 763/// Floating point sine. 764HANDLE_TARGET_OPCODE(G_FSIN) 765 766/// Floating point square root. 767HANDLE_TARGET_OPCODE(G_FSQRT) 768 769/// Floating point floor. 770HANDLE_TARGET_OPCODE(G_FFLOOR) 771 772/// Floating point round to next integer. 773HANDLE_TARGET_OPCODE(G_FRINT) 774 775/// Floating point round to nearest integer. 776HANDLE_TARGET_OPCODE(G_FNEARBYINT) 777 778/// Generic AddressSpaceCast. 779HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 780 781/// Generic block address 782HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 783 784/// Generic jump table address 785HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 786 787/// Generic dynamic stack allocation. 788HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 789 790/// Generic stack pointer save. 791HANDLE_TARGET_OPCODE(G_STACKSAVE) 792 793/// Generic stack pointer restore. 794HANDLE_TARGET_OPCODE(G_STACKRESTORE) 795 796/// Strict floating point instructions. 797HANDLE_TARGET_OPCODE(G_STRICT_FADD) 798HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 799HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 800HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 801HANDLE_TARGET_OPCODE(G_STRICT_FREM) 802HANDLE_TARGET_OPCODE(G_STRICT_FMA) 803HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 804HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP) 805 806/// read_register intrinsic 807HANDLE_TARGET_OPCODE(G_READ_REGISTER) 808 809/// write_register intrinsic 810HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 811 812/// llvm.memcpy intrinsic 813HANDLE_TARGET_OPCODE(G_MEMCPY) 814 815/// llvm.memcpy.inline intrinsic 816HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 817 818/// llvm.memmove intrinsic 819HANDLE_TARGET_OPCODE(G_MEMMOVE) 820 821/// llvm.memset intrinsic 822HANDLE_TARGET_OPCODE(G_MEMSET) 823HANDLE_TARGET_OPCODE(G_BZERO) 824 825/// Vector reductions 826HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 827HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 828HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 829HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 830HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 831HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 832HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM) 833HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM) 834HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 835HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 836HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 837HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 838HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 839HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 840HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 841HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 842HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 843 844HANDLE_TARGET_OPCODE(G_SBFX) 845HANDLE_TARGET_OPCODE(G_UBFX) 846 847/// Marker for the end of the generic opcode. 848/// This is used to check if an opcode is in the range of the 849/// generic opcodes. 850HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 851 852/// BUILTIN_OP_END - This must be the last enum value in this list. 853/// The target-specific post-isel opcode values start here. 854HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 855