1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Precedes a machine instruction to add patchability constraints. An 174/// instruction after PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the following instruction. 177HANDLE_TARGET_OPCODE(PATCHABLE_OP) 178 179/// This is a marker instruction which gets translated into a nop sled, useful 180/// for inserting instrumentation instructions at runtime. 181HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 182 183/// Wraps a return instruction and its operands to enable adding nop sleds 184/// either before or after the return. The nop sleds are useful for inserting 185/// instrumentation instructions at runtime. 186/// The patch here replaces the return instruction. 187HANDLE_TARGET_OPCODE(PATCHABLE_RET) 188 189/// This is a marker instruction which gets translated into a nop sled, useful 190/// for inserting instrumentation instructions at runtime. 191/// The patch here prepends the return instruction. 192/// The same thing as in x86_64 is not possible for ARM because it has multiple 193/// return instructions. Furthermore, CPU allows parametrized and even 194/// conditional return instructions. In the current ARM implementation we are 195/// making use of the fact that currently LLVM doesn't seem to generate 196/// conditional return instructions. 197/// On ARM, the same instruction can be used for popping multiple registers 198/// from the stack and returning (it just pops pc register too), and LLVM 199/// generates it sometimes. So we can't insert the sled between this stack 200/// adjustment and the return without splitting the original instruction into 2 201/// instructions. So on ARM, rather than jumping into the exit trampoline, we 202/// call it, it does the tracing, preserves the stack and returns. 203HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 204 205/// Wraps a tail call instruction and its operands to enable adding nop sleds 206/// either before or after the tail exit. We use this as a disambiguation from 207/// PATCHABLE_RET which specifically only works for return instructions. 208HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 209 210/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 211/// be patched to insert instrumentation instructions. 212HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 213 214/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 215/// can be patched to insert instrumentation instructions. 216HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 217 218HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 219 220// This is a fence with the singlethread scope. It represents a compiler memory 221// barrier, but does not correspond to any generated instruction. 222HANDLE_TARGET_OPCODE(MEMBARRIER) 223 224// Provides information about what jump table the following indirect branch is 225// using. 226HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO) 227 228/// The following generic opcodes are not supposed to appear after ISel. 229/// This is something we might want to relax, but for now, this is convenient 230/// to produce diagnostics. 231 232/// Instructions which should not exist past instruction selection, but do not 233/// generate code. These instructions only act as optimization hints. 234HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 235HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 236HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 237HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 238 G_ASSERT_SEXT) 239HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 240 G_ASSERT_ALIGN) 241 242/// Generic ADD instruction. This is an integer add. 243HANDLE_TARGET_OPCODE(G_ADD) 244HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 245 246/// Generic SUB instruction. This is an integer sub. 247HANDLE_TARGET_OPCODE(G_SUB) 248 249// Generic multiply instruction. 250HANDLE_TARGET_OPCODE(G_MUL) 251 252// Generic signed division instruction. 253HANDLE_TARGET_OPCODE(G_SDIV) 254 255// Generic unsigned division instruction. 256HANDLE_TARGET_OPCODE(G_UDIV) 257 258// Generic signed remainder instruction. 259HANDLE_TARGET_OPCODE(G_SREM) 260 261// Generic unsigned remainder instruction. 262HANDLE_TARGET_OPCODE(G_UREM) 263 264// Generic signed divrem instruction. 265HANDLE_TARGET_OPCODE(G_SDIVREM) 266 267// Generic unsigned divrem instruction. 268HANDLE_TARGET_OPCODE(G_UDIVREM) 269 270/// Generic bitwise and instruction. 271HANDLE_TARGET_OPCODE(G_AND) 272 273/// Generic bitwise or instruction. 274HANDLE_TARGET_OPCODE(G_OR) 275 276/// Generic bitwise exclusive-or instruction. 277HANDLE_TARGET_OPCODE(G_XOR) 278 279 280HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 281 282/// Generic PHI instruction with types. 283HANDLE_TARGET_OPCODE(G_PHI) 284 285/// Generic instruction to materialize the address of an alloca or other 286/// stack-based object. 287HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 288 289/// Generic reference to global value. 290HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 291 292/// Generic instruction to materialize the address of an object in the constant 293/// pool. 294HANDLE_TARGET_OPCODE(G_CONSTANT_POOL) 295 296/// Generic instruction to extract blocks of bits from the register given 297/// (typically a sub-register COPY after instruction selection). 298HANDLE_TARGET_OPCODE(G_EXTRACT) 299 300HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 301 302/// Generic instruction to insert blocks of bits from the registers given into 303/// the source. 304HANDLE_TARGET_OPCODE(G_INSERT) 305 306/// Generic instruction to paste a variable number of components together into a 307/// larger register. 308HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 309 310/// Generic instruction to create a vector value from a number of scalar 311/// components. 312HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 313 314/// Generic instruction to create a vector value from a number of scalar 315/// components, which have types larger than the result vector elt type. 316HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 317 318/// Generic instruction to create a vector by concatenating multiple vectors. 319HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 320 321/// Generic pointer to int conversion. 322HANDLE_TARGET_OPCODE(G_PTRTOINT) 323 324/// Generic int to pointer conversion. 325HANDLE_TARGET_OPCODE(G_INTTOPTR) 326 327/// Generic bitcast. The source and destination types must be different, or a 328/// COPY is the relevant instruction. 329HANDLE_TARGET_OPCODE(G_BITCAST) 330 331/// Generic freeze. 332HANDLE_TARGET_OPCODE(G_FREEZE) 333 334/// Constant folding barrier. 335HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER) 336 337// INTRINSIC fptrunc_round intrinsic. 338HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 339 340/// INTRINSIC trunc intrinsic. 341HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 342 343/// INTRINSIC round intrinsic. 344HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 345 346/// INTRINSIC round to integer intrinsic. 347HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 348 349/// INTRINSIC roundeven intrinsic. 350HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 351 352/// INTRINSIC readcyclecounter 353HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 354 355/// Generic load (including anyext load) 356HANDLE_TARGET_OPCODE(G_LOAD) 357 358/// Generic signext load 359HANDLE_TARGET_OPCODE(G_SEXTLOAD) 360 361/// Generic zeroext load 362HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 363 364/// Generic indexed load (including anyext load) 365HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 366 367/// Generic indexed signext load 368HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 369 370/// Generic indexed zeroext load 371HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 372 373/// Generic store. 374HANDLE_TARGET_OPCODE(G_STORE) 375 376/// Generic indexed store. 377HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 378 379/// Generic atomic cmpxchg with internal success check. 380HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 381 382/// Generic atomic cmpxchg. 383HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 384 385/// Generic atomicrmw. 386HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 387HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 388HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 389HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 390HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 391HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 392HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 393HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 394HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 395HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 396HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 397HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 398HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 399HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 400HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 401HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) 402HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) 403 404// Marker for start of Generic AtomicRMW opcodes 405HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) 406 407// Marker for end of Generic AtomicRMW opcodes 408HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP) 409 410// Generic atomic fence 411HANDLE_TARGET_OPCODE(G_FENCE) 412 413/// Generic prefetch 414HANDLE_TARGET_OPCODE(G_PREFETCH) 415 416/// Generic conditional branch instruction. 417HANDLE_TARGET_OPCODE(G_BRCOND) 418 419/// Generic indirect branch instruction. 420HANDLE_TARGET_OPCODE(G_BRINDIRECT) 421 422/// Begin an invoke region marker. 423HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) 424 425/// Generic intrinsic use (without side effects). 426HANDLE_TARGET_OPCODE(G_INTRINSIC) 427 428/// Generic intrinsic use (with side effects). 429HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 430 431/// Generic intrinsic use (without side effects). 432HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT) 433 434/// Generic intrinsic use (with side effects). 435HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) 436 437/// Generic extension allowing rubbish in high bits. 438HANDLE_TARGET_OPCODE(G_ANYEXT) 439 440/// Generic instruction to discard the high bits of a register. This differs 441/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 442/// each element individually, G_EXTRACT will typically discard the high 443/// elements of the vector. 444HANDLE_TARGET_OPCODE(G_TRUNC) 445 446/// Generic integer constant. 447HANDLE_TARGET_OPCODE(G_CONSTANT) 448 449/// Generic floating constant. 450HANDLE_TARGET_OPCODE(G_FCONSTANT) 451 452/// Generic va_start instruction. Stores to its one pointer operand. 453HANDLE_TARGET_OPCODE(G_VASTART) 454 455/// Generic va_arg instruction. Stores to its one pointer operand. 456HANDLE_TARGET_OPCODE(G_VAARG) 457 458// Generic sign extend 459HANDLE_TARGET_OPCODE(G_SEXT) 460HANDLE_TARGET_OPCODE(G_SEXT_INREG) 461 462// Generic zero extend 463HANDLE_TARGET_OPCODE(G_ZEXT) 464 465// Generic left-shift 466HANDLE_TARGET_OPCODE(G_SHL) 467 468// Generic logical right-shift 469HANDLE_TARGET_OPCODE(G_LSHR) 470 471// Generic arithmetic right-shift 472HANDLE_TARGET_OPCODE(G_ASHR) 473 474// Generic funnel left shift 475HANDLE_TARGET_OPCODE(G_FSHL) 476 477// Generic funnel right shift 478HANDLE_TARGET_OPCODE(G_FSHR) 479 480// Generic right rotate 481HANDLE_TARGET_OPCODE(G_ROTR) 482 483// Generic left rotate 484HANDLE_TARGET_OPCODE(G_ROTL) 485 486/// Generic integer-base comparison, also applicable to vectors of integers. 487HANDLE_TARGET_OPCODE(G_ICMP) 488 489/// Generic floating-point comparison, also applicable to vectors. 490HANDLE_TARGET_OPCODE(G_FCMP) 491 492/// Generic select. 493HANDLE_TARGET_OPCODE(G_SELECT) 494 495/// Generic unsigned add instruction, consuming the normal operands and 496/// producing the result and a carry flag. 497HANDLE_TARGET_OPCODE(G_UADDO) 498 499/// Generic unsigned add instruction, consuming the normal operands plus a carry 500/// flag, and similarly producing the result and a carry flag. 501HANDLE_TARGET_OPCODE(G_UADDE) 502 503/// Generic unsigned sub instruction, consuming the normal operands and 504/// producing the result and a carry flag. 505HANDLE_TARGET_OPCODE(G_USUBO) 506 507/// Generic unsigned subtract instruction, consuming the normal operands plus a 508/// carry flag, and similarly producing the result and a carry flag. 509HANDLE_TARGET_OPCODE(G_USUBE) 510 511/// Generic signed add instruction, producing the result and a signed overflow 512/// flag. 513HANDLE_TARGET_OPCODE(G_SADDO) 514 515/// Generic signed add instruction, consuming the normal operands plus a carry 516/// flag, and similarly producing the result and a carry flag. 517HANDLE_TARGET_OPCODE(G_SADDE) 518 519/// Generic signed subtract instruction, producing the result and a signed 520/// overflow flag. 521HANDLE_TARGET_OPCODE(G_SSUBO) 522 523/// Generic signed sub instruction, consuming the normal operands plus a carry 524/// flag, and similarly producing the result and a carry flag. 525HANDLE_TARGET_OPCODE(G_SSUBE) 526 527/// Generic unsigned multiply instruction, producing the result and a signed 528/// overflow flag. 529HANDLE_TARGET_OPCODE(G_UMULO) 530 531/// Generic signed multiply instruction, producing the result and a signed 532/// overflow flag. 533HANDLE_TARGET_OPCODE(G_SMULO) 534 535// Multiply two numbers at twice the incoming bit width (unsigned) and return 536// the high half of the result. 537HANDLE_TARGET_OPCODE(G_UMULH) 538 539// Multiply two numbers at twice the incoming bit width (signed) and return 540// the high half of the result. 541HANDLE_TARGET_OPCODE(G_SMULH) 542 543/// Generic saturating unsigned addition. 544HANDLE_TARGET_OPCODE(G_UADDSAT) 545 546/// Generic saturating signed addition. 547HANDLE_TARGET_OPCODE(G_SADDSAT) 548 549/// Generic saturating unsigned subtraction. 550HANDLE_TARGET_OPCODE(G_USUBSAT) 551 552/// Generic saturating signed subtraction. 553HANDLE_TARGET_OPCODE(G_SSUBSAT) 554 555/// Generic saturating unsigned left shift. 556HANDLE_TARGET_OPCODE(G_USHLSAT) 557 558/// Generic saturating signed left shift. 559HANDLE_TARGET_OPCODE(G_SSHLSAT) 560 561// Perform signed fixed point multiplication 562HANDLE_TARGET_OPCODE(G_SMULFIX) 563 564// Perform unsigned fixed point multiplication 565HANDLE_TARGET_OPCODE(G_UMULFIX) 566 567// Perform signed, saturating fixed point multiplication 568HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 569 570// Perform unsigned, saturating fixed point multiplication 571HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 572 573// Perform signed fixed point division 574HANDLE_TARGET_OPCODE(G_SDIVFIX) 575 576// Perform unsigned fixed point division 577HANDLE_TARGET_OPCODE(G_UDIVFIX) 578 579// Perform signed, saturating fixed point division 580HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 581 582// Perform unsigned, saturating fixed point division 583HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 584 585/// Generic FP addition. 586HANDLE_TARGET_OPCODE(G_FADD) 587 588/// Generic FP subtraction. 589HANDLE_TARGET_OPCODE(G_FSUB) 590 591/// Generic FP multiplication. 592HANDLE_TARGET_OPCODE(G_FMUL) 593 594/// Generic FMA multiplication. Behaves like llvm fma intrinsic 595HANDLE_TARGET_OPCODE(G_FMA) 596 597/// Generic FP multiply and add. Behaves as separate fmul and fadd. 598HANDLE_TARGET_OPCODE(G_FMAD) 599 600/// Generic FP division. 601HANDLE_TARGET_OPCODE(G_FDIV) 602 603/// Generic FP remainder. 604HANDLE_TARGET_OPCODE(G_FREM) 605 606/// Generic FP exponentiation. 607HANDLE_TARGET_OPCODE(G_FPOW) 608 609/// Generic FP exponentiation, with an integer exponent. 610HANDLE_TARGET_OPCODE(G_FPOWI) 611 612/// Generic base-e exponential of a value. 613HANDLE_TARGET_OPCODE(G_FEXP) 614 615/// Generic base-2 exponential of a value. 616HANDLE_TARGET_OPCODE(G_FEXP2) 617 618/// Generic base-10 exponential of a value. 619HANDLE_TARGET_OPCODE(G_FEXP10) 620 621/// Floating point base-e logarithm of a value. 622HANDLE_TARGET_OPCODE(G_FLOG) 623 624/// Floating point base-2 logarithm of a value. 625HANDLE_TARGET_OPCODE(G_FLOG2) 626 627/// Floating point base-10 logarithm of a value. 628HANDLE_TARGET_OPCODE(G_FLOG10) 629 630/// Floating point x * 2^n 631HANDLE_TARGET_OPCODE(G_FLDEXP) 632 633/// Floating point extract fraction and exponent. 634HANDLE_TARGET_OPCODE(G_FFREXP) 635 636/// Generic FP negation. 637HANDLE_TARGET_OPCODE(G_FNEG) 638 639/// Generic FP extension. 640HANDLE_TARGET_OPCODE(G_FPEXT) 641 642/// Generic float to signed-int conversion 643HANDLE_TARGET_OPCODE(G_FPTRUNC) 644 645/// Generic float to signed-int conversion 646HANDLE_TARGET_OPCODE(G_FPTOSI) 647 648/// Generic float to unsigned-int conversion 649HANDLE_TARGET_OPCODE(G_FPTOUI) 650 651/// Generic signed-int to float conversion 652HANDLE_TARGET_OPCODE(G_SITOFP) 653 654/// Generic unsigned-int to float conversion 655HANDLE_TARGET_OPCODE(G_UITOFP) 656 657/// Generic FP absolute value. 658HANDLE_TARGET_OPCODE(G_FABS) 659 660/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 661/// not require that X and Y have the same type, just that they are both 662/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 663/// f64) is allowed. 664HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 665 666/// Generic test for floating-point class. 667HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 668 669/// Generic FP canonicalize value. 670HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 671 672/// FP min/max matching libm's fmin/fmax 673HANDLE_TARGET_OPCODE(G_FMINNUM) 674HANDLE_TARGET_OPCODE(G_FMAXNUM) 675 676/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 677HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 678HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 679 680/// FP min/max matching IEEE-754 2018 draft semantics. 681HANDLE_TARGET_OPCODE(G_FMINIMUM) 682HANDLE_TARGET_OPCODE(G_FMAXIMUM) 683 684/// Access to FP environment. 685HANDLE_TARGET_OPCODE(G_GET_FPENV) 686HANDLE_TARGET_OPCODE(G_SET_FPENV) 687HANDLE_TARGET_OPCODE(G_RESET_FPENV) 688HANDLE_TARGET_OPCODE(G_GET_FPMODE) 689HANDLE_TARGET_OPCODE(G_SET_FPMODE) 690HANDLE_TARGET_OPCODE(G_RESET_FPMODE) 691 692/// Generic pointer offset 693HANDLE_TARGET_OPCODE(G_PTR_ADD) 694 695/// Clear the specified bits in a pointer. 696HANDLE_TARGET_OPCODE(G_PTRMASK) 697 698/// Generic signed integer minimum. 699HANDLE_TARGET_OPCODE(G_SMIN) 700 701/// Generic signed integer maximum. 702HANDLE_TARGET_OPCODE(G_SMAX) 703 704/// Generic unsigned integer maximum. 705HANDLE_TARGET_OPCODE(G_UMIN) 706 707/// Generic unsigned integer maximum. 708HANDLE_TARGET_OPCODE(G_UMAX) 709 710/// Generic integer absolute value. 711HANDLE_TARGET_OPCODE(G_ABS) 712 713HANDLE_TARGET_OPCODE(G_LROUND) 714HANDLE_TARGET_OPCODE(G_LLROUND) 715 716/// Generic BRANCH instruction. This is an unconditional branch. 717HANDLE_TARGET_OPCODE(G_BR) 718 719/// Generic branch to jump table entry. 720HANDLE_TARGET_OPCODE(G_BRJT) 721 722/// Generic insertelement. 723HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 724 725/// Generic extractelement. 726HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 727 728/// Generic shufflevector. 729HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 730 731/// Generic count trailing zeroes. 732HANDLE_TARGET_OPCODE(G_CTTZ) 733 734/// Same as above, undefined for zero inputs. 735HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 736 737/// Generic count leading zeroes. 738HANDLE_TARGET_OPCODE(G_CTLZ) 739 740/// Same as above, undefined for zero inputs. 741HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 742 743/// Generic count bits. 744HANDLE_TARGET_OPCODE(G_CTPOP) 745 746/// Generic byte swap. 747HANDLE_TARGET_OPCODE(G_BSWAP) 748 749/// Generic bit reverse. 750HANDLE_TARGET_OPCODE(G_BITREVERSE) 751 752/// Floating point ceil. 753HANDLE_TARGET_OPCODE(G_FCEIL) 754 755/// Floating point cosine. 756HANDLE_TARGET_OPCODE(G_FCOS) 757 758/// Floating point sine. 759HANDLE_TARGET_OPCODE(G_FSIN) 760 761/// Floating point square root. 762HANDLE_TARGET_OPCODE(G_FSQRT) 763 764/// Floating point floor. 765HANDLE_TARGET_OPCODE(G_FFLOOR) 766 767/// Floating point round to next integer. 768HANDLE_TARGET_OPCODE(G_FRINT) 769 770/// Floating point round to nearest integer. 771HANDLE_TARGET_OPCODE(G_FNEARBYINT) 772 773/// Generic AddressSpaceCast. 774HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 775 776/// Generic block address 777HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 778 779/// Generic jump table address 780HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 781 782/// Generic dynamic stack allocation. 783HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 784 785/// Generic stack pointer save. 786HANDLE_TARGET_OPCODE(G_STACKSAVE) 787 788/// Generic stack pointer restore. 789HANDLE_TARGET_OPCODE(G_STACKRESTORE) 790 791/// Strict floating point instructions. 792HANDLE_TARGET_OPCODE(G_STRICT_FADD) 793HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 794HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 795HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 796HANDLE_TARGET_OPCODE(G_STRICT_FREM) 797HANDLE_TARGET_OPCODE(G_STRICT_FMA) 798HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 799HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP) 800 801/// read_register intrinsic 802HANDLE_TARGET_OPCODE(G_READ_REGISTER) 803 804/// write_register intrinsic 805HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 806 807/// llvm.memcpy intrinsic 808HANDLE_TARGET_OPCODE(G_MEMCPY) 809 810/// llvm.memcpy.inline intrinsic 811HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 812 813/// llvm.memmove intrinsic 814HANDLE_TARGET_OPCODE(G_MEMMOVE) 815 816/// llvm.memset intrinsic 817HANDLE_TARGET_OPCODE(G_MEMSET) 818HANDLE_TARGET_OPCODE(G_BZERO) 819 820/// Vector reductions 821HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 822HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 823HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 824HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 825HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 826HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 827HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM) 828HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM) 829HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 830HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 831HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 832HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 833HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 834HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 835HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 836HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 837HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 838 839HANDLE_TARGET_OPCODE(G_SBFX) 840HANDLE_TARGET_OPCODE(G_UBFX) 841 842/// Marker for the end of the generic opcode. 843/// This is used to check if an opcode is in the range of the 844/// generic opcodes. 845HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 846 847/// BUILTIN_OP_END - This must be the last enum value in this list. 848/// The target-specific post-isel opcode values start here. 849HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 850