1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 81HANDLE_TARGET_OPCODE(DBG_LABEL) 82 83/// REG_SEQUENCE - This variadic instruction is used to form a register that 84/// represents a consecutive sequence of sub-registers. It's used as a 85/// register coalescing / allocation aid and must be eliminated before code 86/// emission. 87// In SDNode form, the first operand encodes the register class created by 88// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 89// pair. Once it has been lowered to a MachineInstr, the regclass operand 90// is no longer present. 91/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 92/// After register coalescing references of v1024 should be replace with 93/// v1027:3, v1025 with v1027:4, etc. 94 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 95 96/// COPY - Target-independent register copy. This instruction can also be 97/// used to copy between subregisters of virtual registers. 98 HANDLE_TARGET_OPCODE(COPY) 99 100/// BUNDLE - This instruction represents an instruction bundle. Instructions 101/// which immediately follow a BUNDLE instruction which are marked with 102/// 'InsideBundle' flag are inside the bundle. 103HANDLE_TARGET_OPCODE(BUNDLE) 104 105/// Lifetime markers. 106HANDLE_TARGET_OPCODE(LIFETIME_START) 107HANDLE_TARGET_OPCODE(LIFETIME_END) 108 109/// A Stackmap instruction captures the location of live variables at its 110/// position in the instruction stream. It is followed by a shadow of bytes 111/// that must lie within the function and not contain another stackmap. 112HANDLE_TARGET_OPCODE(STACKMAP) 113 114/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 115HANDLE_TARGET_OPCODE(FENTRY_CALL) 116 117/// Patchable call instruction - this instruction represents a call to a 118/// constant address, followed by a series of NOPs. It is intended to 119/// support optimizations for dynamic languages (such as javascript) that 120/// rewrite calls to runtimes with more efficient code sequences. 121/// This also implies a stack map. 122HANDLE_TARGET_OPCODE(PATCHPOINT) 123 124/// This pseudo-instruction loads the stack guard value. Targets which need 125/// to prevent the stack guard value or address from being spilled to the 126/// stack should override TargetLowering::emitLoadStackGuardNode and 127/// additionally expand this pseudo after register allocation. 128HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 129 130/// Call instruction with associated vm state for deoptimization and list 131/// of live pointers for relocation by the garbage collector. It is 132/// intended to support garbage collection with fully precise relocating 133/// collectors and deoptimizations in either the callee or caller. 134HANDLE_TARGET_OPCODE(STATEPOINT) 135 136/// Instruction that records the offset of a local stack allocation passed to 137/// llvm.localescape. It has two arguments: the symbol for the label and the 138/// frame index of the local stack allocation. 139HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 140 141/// Wraps a machine instruction which can fault, bundled with associated 142/// information on how to handle such a fault. 143/// For example loading instruction that may page fault, bundled with associated 144/// information on how to handle such a page fault. It is intended to support 145/// "zero cost" null checks in managed languages by allowing LLVM to fold 146/// comparisons into existing memory operations. 147HANDLE_TARGET_OPCODE(FAULTING_OP) 148 149/// Wraps a machine instruction to add patchability constraints. An 150/// instruction wrapped in PATCHABLE_OP has to either have a minimum 151/// size or be preceded with a nop of that size. The first operand is 152/// an immediate denoting the minimum size of the instruction, the 153/// second operand is an immediate denoting the opcode of the original 154/// instruction. The rest of the operands are the operands of the 155/// original instruction. 156HANDLE_TARGET_OPCODE(PATCHABLE_OP) 157 158/// This is a marker instruction which gets translated into a nop sled, useful 159/// for inserting instrumentation instructions at runtime. 160HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 161 162/// Wraps a return instruction and its operands to enable adding nop sleds 163/// either before or after the return. The nop sleds are useful for inserting 164/// instrumentation instructions at runtime. 165/// The patch here replaces the return instruction. 166HANDLE_TARGET_OPCODE(PATCHABLE_RET) 167 168/// This is a marker instruction which gets translated into a nop sled, useful 169/// for inserting instrumentation instructions at runtime. 170/// The patch here prepends the return instruction. 171/// The same thing as in x86_64 is not possible for ARM because it has multiple 172/// return instructions. Furthermore, CPU allows parametrized and even 173/// conditional return instructions. In the current ARM implementation we are 174/// making use of the fact that currently LLVM doesn't seem to generate 175/// conditional return instructions. 176/// On ARM, the same instruction can be used for popping multiple registers 177/// from the stack and returning (it just pops pc register too), and LLVM 178/// generates it sometimes. So we can't insert the sled between this stack 179/// adjustment and the return without splitting the original instruction into 2 180/// instructions. So on ARM, rather than jumping into the exit trampoline, we 181/// call it, it does the tracing, preserves the stack and returns. 182HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 183 184/// Wraps a tail call instruction and its operands to enable adding nop sleds 185/// either before or after the tail exit. We use this as a disambiguation from 186/// PATCHABLE_RET which specifically only works for return instructions. 187HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 188 189/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 190/// be patched to insert instrumentation instructions. 191HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 192 193/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 194/// can be patched to insert instrumentation instructions. 195HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 196 197HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 198 199/// The following generic opcodes are not supposed to appear after ISel. 200/// This is something we might want to relax, but for now, this is convenient 201/// to produce diagnostics. 202 203/// Generic ADD instruction. This is an integer add. 204HANDLE_TARGET_OPCODE(G_ADD) 205HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 206 207/// Generic SUB instruction. This is an integer sub. 208HANDLE_TARGET_OPCODE(G_SUB) 209 210// Generic multiply instruction. 211HANDLE_TARGET_OPCODE(G_MUL) 212 213// Generic signed division instruction. 214HANDLE_TARGET_OPCODE(G_SDIV) 215 216// Generic unsigned division instruction. 217HANDLE_TARGET_OPCODE(G_UDIV) 218 219// Generic signed remainder instruction. 220HANDLE_TARGET_OPCODE(G_SREM) 221 222// Generic unsigned remainder instruction. 223HANDLE_TARGET_OPCODE(G_UREM) 224 225/// Generic bitwise and instruction. 226HANDLE_TARGET_OPCODE(G_AND) 227 228/// Generic bitwise or instruction. 229HANDLE_TARGET_OPCODE(G_OR) 230 231/// Generic bitwise exclusive-or instruction. 232HANDLE_TARGET_OPCODE(G_XOR) 233 234 235HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 236 237/// Generic PHI instruction with types. 238HANDLE_TARGET_OPCODE(G_PHI) 239 240/// Generic instruction to materialize the address of an alloca or other 241/// stack-based object. 242HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 243 244/// Generic reference to global value. 245HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 246 247/// Generic instruction to extract blocks of bits from the register given 248/// (typically a sub-register COPY after instruction selection). 249HANDLE_TARGET_OPCODE(G_EXTRACT) 250 251HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 252 253/// Generic instruction to insert blocks of bits from the registers given into 254/// the source. 255HANDLE_TARGET_OPCODE(G_INSERT) 256 257/// Generic instruction to paste a variable number of components together into a 258/// larger register. 259HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 260 261/// Generic instruction to create a vector value from a number of scalar 262/// components. 263HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 264 265/// Generic instruction to create a vector value from a number of scalar 266/// components, which have types larger than the result vector elt type. 267HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 268 269/// Generic instruction to create a vector by concatenating multiple vectors. 270HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 271 272/// Generic pointer to int conversion. 273HANDLE_TARGET_OPCODE(G_PTRTOINT) 274 275/// Generic int to pointer conversion. 276HANDLE_TARGET_OPCODE(G_INTTOPTR) 277 278/// Generic bitcast. The source and destination types must be different, or a 279/// COPY is the relevant instruction. 280HANDLE_TARGET_OPCODE(G_BITCAST) 281 282/// INTRINSIC trunc intrinsic. 283HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 284 285/// INTRINSIC round intrinsic. 286HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 287 288/// Generic load (including anyext load) 289HANDLE_TARGET_OPCODE(G_LOAD) 290 291/// Generic signext load 292HANDLE_TARGET_OPCODE(G_SEXTLOAD) 293 294/// Generic zeroext load 295HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 296 297/// Generic store. 298HANDLE_TARGET_OPCODE(G_STORE) 299 300/// Generic atomic cmpxchg with internal success check. 301HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 302 303/// Generic atomic cmpxchg. 304HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 305 306/// Generic atomicrmw. 307HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 308HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 309HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 310HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 311HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 312HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 313HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 314HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 315HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 316HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 317HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 318 319// Generic atomic fence 320HANDLE_TARGET_OPCODE(G_FENCE) 321 322/// Generic conditional branch instruction. 323HANDLE_TARGET_OPCODE(G_BRCOND) 324 325/// Generic indirect branch instruction. 326HANDLE_TARGET_OPCODE(G_BRINDIRECT) 327 328/// Generic intrinsic use (without side effects). 329HANDLE_TARGET_OPCODE(G_INTRINSIC) 330 331/// Generic intrinsic use (with side effects). 332HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 333 334/// Generic extension allowing rubbish in high bits. 335HANDLE_TARGET_OPCODE(G_ANYEXT) 336 337/// Generic instruction to discard the high bits of a register. This differs 338/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 339/// each element individually, G_EXTRACT will typically discard the high 340/// elements of the vector. 341HANDLE_TARGET_OPCODE(G_TRUNC) 342 343/// Generic integer constant. 344HANDLE_TARGET_OPCODE(G_CONSTANT) 345 346/// Generic floating constant. 347HANDLE_TARGET_OPCODE(G_FCONSTANT) 348 349/// Generic va_start instruction. Stores to its one pointer operand. 350HANDLE_TARGET_OPCODE(G_VASTART) 351 352/// Generic va_start instruction. Stores to its one pointer operand. 353HANDLE_TARGET_OPCODE(G_VAARG) 354 355// Generic sign extend 356HANDLE_TARGET_OPCODE(G_SEXT) 357 358// Generic zero extend 359HANDLE_TARGET_OPCODE(G_ZEXT) 360 361// Generic left-shift 362HANDLE_TARGET_OPCODE(G_SHL) 363 364// Generic logical right-shift 365HANDLE_TARGET_OPCODE(G_LSHR) 366 367// Generic arithmetic right-shift 368HANDLE_TARGET_OPCODE(G_ASHR) 369 370/// Generic integer-base comparison, also applicable to vectors of integers. 371HANDLE_TARGET_OPCODE(G_ICMP) 372 373/// Generic floating-point comparison, also applicable to vectors. 374HANDLE_TARGET_OPCODE(G_FCMP) 375 376/// Generic select. 377HANDLE_TARGET_OPCODE(G_SELECT) 378 379/// Generic unsigned add instruction, consuming the normal operands and 380/// producing the result and a carry flag. 381HANDLE_TARGET_OPCODE(G_UADDO) 382 383/// Generic unsigned add instruction, consuming the normal operands plus a carry 384/// flag, and similarly producing the result and a carry flag. 385HANDLE_TARGET_OPCODE(G_UADDE) 386 387/// Generic unsigned sub instruction, consuming the normal operands and 388/// producing the result and a carry flag. 389HANDLE_TARGET_OPCODE(G_USUBO) 390 391/// Generic unsigned subtract instruction, consuming the normal operands plus a 392/// carry flag, and similarly producing the result and a carry flag. 393HANDLE_TARGET_OPCODE(G_USUBE) 394 395/// Generic signed add instruction, producing the result and a signed overflow 396/// flag. 397HANDLE_TARGET_OPCODE(G_SADDO) 398 399/// Generic signed add instruction, consuming the normal operands plus a carry 400/// flag, and similarly producing the result and a carry flag. 401HANDLE_TARGET_OPCODE(G_SADDE) 402 403/// Generic signed subtract instruction, producing the result and a signed 404/// overflow flag. 405HANDLE_TARGET_OPCODE(G_SSUBO) 406 407/// Generic signed sub instruction, consuming the normal operands plus a carry 408/// flag, and similarly producing the result and a carry flag. 409HANDLE_TARGET_OPCODE(G_SSUBE) 410 411/// Generic unsigned multiply instruction, producing the result and a signed 412/// overflow flag. 413HANDLE_TARGET_OPCODE(G_UMULO) 414 415/// Generic signed multiply instruction, producing the result and a signed 416/// overflow flag. 417HANDLE_TARGET_OPCODE(G_SMULO) 418 419// Multiply two numbers at twice the incoming bit width (unsigned) and return 420// the high half of the result. 421HANDLE_TARGET_OPCODE(G_UMULH) 422 423// Multiply two numbers at twice the incoming bit width (signed) and return 424// the high half of the result. 425HANDLE_TARGET_OPCODE(G_SMULH) 426 427/// Generic FP addition. 428HANDLE_TARGET_OPCODE(G_FADD) 429 430/// Generic FP subtraction. 431HANDLE_TARGET_OPCODE(G_FSUB) 432 433/// Generic FP multiplication. 434HANDLE_TARGET_OPCODE(G_FMUL) 435 436/// Generic FMA multiplication. Behaves like llvm fma intrinsic 437HANDLE_TARGET_OPCODE(G_FMA) 438 439/// Generic FP division. 440HANDLE_TARGET_OPCODE(G_FDIV) 441 442/// Generic FP remainder. 443HANDLE_TARGET_OPCODE(G_FREM) 444 445/// Generic FP exponentiation. 446HANDLE_TARGET_OPCODE(G_FPOW) 447 448/// Generic base-e exponential of a value. 449HANDLE_TARGET_OPCODE(G_FEXP) 450 451/// Generic base-2 exponential of a value. 452HANDLE_TARGET_OPCODE(G_FEXP2) 453 454/// Floating point base-e logarithm of a value. 455HANDLE_TARGET_OPCODE(G_FLOG) 456 457/// Floating point base-2 logarithm of a value. 458HANDLE_TARGET_OPCODE(G_FLOG2) 459 460/// Floating point base-10 logarithm of a value. 461HANDLE_TARGET_OPCODE(G_FLOG10) 462 463/// Generic FP negation. 464HANDLE_TARGET_OPCODE(G_FNEG) 465 466/// Generic FP extension. 467HANDLE_TARGET_OPCODE(G_FPEXT) 468 469/// Generic float to signed-int conversion 470HANDLE_TARGET_OPCODE(G_FPTRUNC) 471 472/// Generic float to signed-int conversion 473HANDLE_TARGET_OPCODE(G_FPTOSI) 474 475/// Generic float to unsigned-int conversion 476HANDLE_TARGET_OPCODE(G_FPTOUI) 477 478/// Generic signed-int to float conversion 479HANDLE_TARGET_OPCODE(G_SITOFP) 480 481/// Generic unsigned-int to float conversion 482HANDLE_TARGET_OPCODE(G_UITOFP) 483 484/// Generic FP absolute value. 485HANDLE_TARGET_OPCODE(G_FABS) 486 487/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 488/// not require that X and Y have the same type, just that they are both 489/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 490/// f64) is allowed. 491HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 492 493/// Generic FP canonicalize value. 494HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 495 496/// FP min/max matching libm's fmin/fmax 497HANDLE_TARGET_OPCODE(G_FMINNUM) 498HANDLE_TARGET_OPCODE(G_FMAXNUM) 499 500/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 501HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 502HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 503 504/// FP min/max matching IEEE-754 2018 draft semantics. 505HANDLE_TARGET_OPCODE(G_FMINIMUM) 506HANDLE_TARGET_OPCODE(G_FMAXIMUM) 507 508/// Generic pointer offset 509HANDLE_TARGET_OPCODE(G_GEP) 510 511/// Clear the specified number of low bits in a pointer. This rounds the value 512/// *down* to the given alignment. 513HANDLE_TARGET_OPCODE(G_PTR_MASK) 514 515/// Generic signed integer minimum. 516HANDLE_TARGET_OPCODE(G_SMIN) 517 518/// Generic signed integer maximum. 519HANDLE_TARGET_OPCODE(G_SMAX) 520 521/// Generic unsigned integer maximum. 522HANDLE_TARGET_OPCODE(G_UMIN) 523 524/// Generic unsigned integer maximum. 525HANDLE_TARGET_OPCODE(G_UMAX) 526 527/// Generic BRANCH instruction. This is an unconditional branch. 528HANDLE_TARGET_OPCODE(G_BR) 529 530/// Generic branch to jump table entry. 531HANDLE_TARGET_OPCODE(G_BRJT) 532 533/// Generic insertelement. 534HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 535 536/// Generic extractelement. 537HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 538 539/// Generic shufflevector. 540HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 541 542/// Generic count trailing zeroes. 543HANDLE_TARGET_OPCODE(G_CTTZ) 544 545/// Same as above, undefined for zero inputs. 546HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 547 548/// Generic count leading zeroes. 549HANDLE_TARGET_OPCODE(G_CTLZ) 550 551/// Same as above, undefined for zero inputs. 552HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 553 554/// Generic count bits. 555HANDLE_TARGET_OPCODE(G_CTPOP) 556 557/// Generic byte swap. 558HANDLE_TARGET_OPCODE(G_BSWAP) 559 560/// Floating point ceil. 561HANDLE_TARGET_OPCODE(G_FCEIL) 562 563/// Floating point cosine. 564HANDLE_TARGET_OPCODE(G_FCOS) 565 566/// Floating point sine. 567HANDLE_TARGET_OPCODE(G_FSIN) 568 569/// Floating point square root. 570HANDLE_TARGET_OPCODE(G_FSQRT) 571 572/// Floating point floor. 573HANDLE_TARGET_OPCODE(G_FFLOOR) 574 575/// Floating point round to next integer. 576HANDLE_TARGET_OPCODE(G_FRINT) 577 578/// Floating point round to nearest integer. 579HANDLE_TARGET_OPCODE(G_FNEARBYINT) 580 581/// Generic AddressSpaceCast. 582HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 583 584/// Generic block address 585HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 586 587/// Generic jump table address 588HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 589 590// TODO: Add more generic opcodes as we move along. 591 592/// Marker for the end of the generic opcode. 593/// This is used to check if an opcode is in the range of the 594/// generic opcodes. 595HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_JUMP_TABLE) 596 597/// BUILTIN_OP_END - This must be the last enum value in this list. 598/// The target-specific post-isel opcode values start here. 599HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 600