1*06c3fb27SDimitry Andric//===- IntrinsicsRISCVXTHead.td - T-Head intrinsics --------*- tablegen -*-===// 2*06c3fb27SDimitry Andric// 3*06c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*06c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*06c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*06c3fb27SDimitry Andric// 7*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 8*06c3fb27SDimitry Andric// 9*06c3fb27SDimitry Andric// This file defines all of the T-Head vendor intrinsics for RISC-V. 10*06c3fb27SDimitry Andric// 11*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 12*06c3fb27SDimitry Andric 13bdd1243dSDimitry Andriclet TargetPrefix = "riscv" in { 14bdd1243dSDimitry Andric 15bdd1243dSDimitry Andric class TH_VdotTernaryWideMasked 16bdd1243dSDimitry Andric : DefaultAttrsIntrinsic< [llvm_anyvector_ty], 17bdd1243dSDimitry Andric [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, 18bdd1243dSDimitry Andric LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>, 19bdd1243dSDimitry Andric llvm_anyint_ty, LLVMMatchType<3>], 20bdd1243dSDimitry Andric [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic { 21bdd1243dSDimitry Andric let ScalarOperand = 1; 22bdd1243dSDimitry Andric let VLOperand = 4; 23bdd1243dSDimitry Andric } 24bdd1243dSDimitry Andric 25bdd1243dSDimitry Andric multiclass TH_VdotTernaryWide { 26bdd1243dSDimitry Andric def "int_riscv_" # NAME : RISCVTernaryWideUnMasked; 27bdd1243dSDimitry Andric def "int_riscv_" # NAME # "_mask" : TH_VdotTernaryWideMasked; 28bdd1243dSDimitry Andric } 29bdd1243dSDimitry Andric 30bdd1243dSDimitry Andric defm th_vmaqa : TH_VdotTernaryWide; 31bdd1243dSDimitry Andric defm th_vmaqau : TH_VdotTernaryWide; 32bdd1243dSDimitry Andric defm th_vmaqasu : TH_VdotTernaryWide; 33bdd1243dSDimitry Andric defm th_vmaqaus : TH_VdotTernaryWide; 34bdd1243dSDimitry Andric} 35